Loading drivers/power/supply/qcom/qpnp-qg.c +12 −0 Original line number Diff line number Diff line Loading @@ -2277,6 +2277,17 @@ static const struct power_supply_desc qg_psy_desc = { .property_is_writeable = qg_property_is_writeable, }; #define DEFAULT_CL_BEGIN_IBAT_UA (-100000) static bool qg_cl_ok_to_begin(void *data) { struct qpnp_qg *chip = data; if (chip->last_fifo_i_ua < DEFAULT_CL_BEGIN_IBAT_UA) return true; return false; } #define DEFAULT_RECHARGE_SOC 95 static int qg_charge_full_update(struct qpnp_qg *chip) { Loading Loading @@ -3752,6 +3763,7 @@ static int qg_alg_init(struct qpnp_qg *chip) cl->get_cc_soc = qg_get_cc_soc; cl->get_learned_capacity = qg_get_learned_capacity; cl->store_learned_capacity = qg_store_learned_capacity; cl->ok_to_begin = qg_cl_ok_to_begin; cl->data = chip; rc = cap_learning_init(cl); Loading Loading
drivers/power/supply/qcom/qpnp-qg.c +12 −0 Original line number Diff line number Diff line Loading @@ -2277,6 +2277,17 @@ static const struct power_supply_desc qg_psy_desc = { .property_is_writeable = qg_property_is_writeable, }; #define DEFAULT_CL_BEGIN_IBAT_UA (-100000) static bool qg_cl_ok_to_begin(void *data) { struct qpnp_qg *chip = data; if (chip->last_fifo_i_ua < DEFAULT_CL_BEGIN_IBAT_UA) return true; return false; } #define DEFAULT_RECHARGE_SOC 95 static int qg_charge_full_update(struct qpnp_qg *chip) { Loading Loading @@ -3752,6 +3763,7 @@ static int qg_alg_init(struct qpnp_qg *chip) cl->get_cc_soc = qg_get_cc_soc; cl->get_learned_capacity = qg_get_learned_capacity; cl->store_learned_capacity = qg_store_learned_capacity; cl->ok_to_begin = qg_cl_ok_to_begin; cl->data = chip; rc = cap_learning_init(cl); Loading