Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 88464279 authored by Paolo Bonzini's avatar Paolo Bonzini Committed by Greg Kroah-Hartman
Browse files

KVM: SVM: relax conditions for allowing MSR_IA32_SPEC_CTRL accesses 



[ Upstream commit df7e8818926eb4712b67421442acf7d568fe2645 ]

Userspace that does not know about the AMD_IBRS bit might still
allow the guest to protect itself with MSR_IA32_SPEC_CTRL using
the Intel SPEC_CTRL bit.  However, svm.c disallows this and will
cause a #GP in the guest when writing to the MSR.  Fix this by
loosening the test and allowing the Intel CPUID bit, and in fact
allow the AMD_STIBP bit as well since it allows writing to
MSR_IA32_SPEC_CTRL too.

Reported-by: default avatarZhiyi Guo <zhguo@redhat.com>
Analyzed-by: default avatarDr. David Alan Gilbert <dgilbert@redhat.com>
Analyzed-by: default avatarLaszlo Ersek <lersek@redhat.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent c1f49fb1

arch/x86/kvm/svm.c

+4 −0
Original line number Diff line number Diff line
@@ -4209,6 +4209,8 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) 
		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr_info->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))

			return 1;
@@ -4312,6 +4314,8 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr) 
		break;

	case MSR_IA32_SPEC_CTRL:

		if (!msr->host_initiated &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&

		    !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))

			return 1;