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Commit 88076015 authored by Sara Sharon's avatar Sara Sharon Committed by Emmanuel Grumbach
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iwlwifi: pcie: configure more RFH settings 



Fine tune RFH registers further:
* Set default queue explicitly
* Set RFH to drop frames exceeding RB size
* Set the maximum rx transfer size to DRAM to 128 instead of 64

Signed-off-by: default avatarSara Sharon <sara.sharon@intel.com>
Signed-off-by: default avatarEmmanuel Grumbach <emmanuel.grumbach@intel.com>
parent 3af512d6

drivers/net/wireless/intel/iwlwifi/iwl-fh.h

+14 −10
Original line number Diff line number Diff line
@@ -6,7 +6,7 @@ 
 * GPL LICENSE SUMMARY

 *

 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.

 * Copyright(c) 2015 Intel Deutschland GmbH

 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of version 2 of the GNU General Public License as
@@ -32,7 +32,7 @@ 
 * BSD LICENSE

 *

 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.

 * Copyright(c) 2015 Intel Deutschland GmbH

 * Copyright(c) 2015 - 2016 Intel Deutschland GmbH

 * All rights reserved.

 *

 * Redistribution and use in source and binary forms, with or without
@@ -371,6 +371,7 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl) 
#define RFH_RXF_DMA_MIN_RB_SIZE_MASK	(0x03000000) /* bit 24-25 */

#define RFH_RXF_DMA_MIN_RB_SIZE_POS	24

#define RFH_RXF_DMA_MIN_RB_4_8		(3 << RFH_RXF_DMA_MIN_RB_SIZE_POS)

#define RFH_RXF_DMA_DROP_TOO_LARGE_MASK	(0x04000000) /* bit 26 */

#define RFH_RXF_DMA_SINGLE_FRAME_MASK	(0x20000000) /* bit 29 */

#define RFH_DMA_EN_MASK			(0xC0000000) /* bits 30-31*/

#define RFH_DMA_EN_ENABLE_VAL		BIT(31)
@@ -378,10 +379,13 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl) 
#define RFH_RXF_RXQ_ACTIVE 0xA0980C



#define RFH_GEN_CFG	0xA09800

#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00

#define RFH_GEN_CFG_SERVICE_DMA_SNOOP	BIT(0)

#define RFH_GEN_CFG_RFH_DMA_SNOOP	BIT(1)

#define DEFAULT_RXQ_NUM 8

#define RFH_GEN_CFG_RB_CHUNK_SIZE	BIT(4) /* 0 - 64B, 1- 128B */

#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00

#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS 8



#define DEFAULT_RXQ_NUM			0



/* end of 9000 rx series registers */

drivers/net/wireless/intel/iwlwifi/pcie/rx.c

+11 −1
Original line number Diff line number Diff line
@@ -783,16 +783,26 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans) 
	 * Single frame mode

	 * Rx buffer size 4 or 8k or 12k

	 * Min RB size 4 or 8

	 * Drop frames that exceed RB size

	 * 512 RBDs

	 */

	iwl_write_prph(trans, RFH_RXF_DMA_CFG,

		       RFH_DMA_EN_ENABLE_VAL |

		       rb_size | RFH_RXF_DMA_SINGLE_FRAME_MASK |

		       RFH_RXF_DMA_MIN_RB_4_8 |

		       RFH_RXF_DMA_DROP_TOO_LARGE_MASK |

		       RFH_RXF_DMA_RBDCB_SIZE_512);



	/*

	 * Activate DMA snooping.

	 * Set RX DMA chunk size to 128 bit

	 * Default queue is 0

	 */

	iwl_write_prph(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP |

		       RFH_GEN_CFG_RB_CHUNK_SIZE |

		       (DEFAULT_RXQ_NUM << RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS) |

		       RFH_GEN_CFG_SERVICE_DMA_SNOOP);

	/* Enable the relevant rx queues */

	iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, enabled);



	/* Set interrupt coalescing timer to default (2048 usecs) */