Loading drivers/gpu/drm/msm/dp/dp_catalog.c +62 −4 Original line number Diff line number Diff line Loading @@ -64,6 +64,11 @@ static u8 const vm_voltage_swing[4][4] = { {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; enum dp_flush_bit { DP_PPS_FLUSH, DP_DHDR_FLUSH, }; struct dp_catalog_io { struct dp_io_data *dp_ahb; struct dp_io_data *dp_aux; Loading Loading @@ -572,14 +577,16 @@ static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel) DUMP_PREFIX_NONE, 16, 4, buf, off, false); } static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en, u32 dhdr_max_pkts) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; u32 cfg, cfg2, misc; u32 cfg, cfg2, cfg4, misc; u32 sdp_cfg_off = 0; u32 sdp_cfg2_off = 0; u32 sdp_cfg3_off = 0; u32 sdp_cfg4_off = 0; u32 misc1_misc0_off = 0; if (!panel) { Loading @@ -599,6 +606,7 @@ static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4; misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0; } Loading @@ -620,6 +628,13 @@ static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2); /* DHDR_EN, DHDR_PACKET_LIMIT */ if (dhdr_max_pkts) { cfg4 = (dhdr_max_pkts << 1) | BIT(0); dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4); } dp_catalog_panel_setup_vsc_sdp(panel); dp_catalog_panel_setup_infoframe_sdp(panel); Loading @@ -641,6 +656,11 @@ static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2); /* DHDR_EN, DHDR_PACKET_LIMIT */ cfg4 = 0; dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4); /* switch back to MSA */ misc &= ~BIT(14); Loading Loading @@ -1192,7 +1212,8 @@ static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel) reg, panel->stream_id); } static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel) static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel, enum dp_flush_bit flush_bit) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; Loading @@ -1217,12 +1238,47 @@ static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel) offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH; dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset); dp_flush |= BIT(0); dp_flush |= BIT(flush_bit); dp_write(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset, dp_flush); } static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel) { dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH); pr_debug("pps flush for stream:%d\n", panel->stream_id); } static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel) { dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH); pr_debug("dhdr flush for stream:%d\n", panel->stream_id); } static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; u32 dp_flush, offset; if (panel->stream_id >= DP_STREAM_MAX) { pr_err("invalid stream_id:%d\n", panel->stream_id); return false; } catalog = dp_catalog_get_priv(panel); io_data = catalog->io.dp_link; if (panel->stream_id == DP_STREAM_0) offset = 0; else offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH; dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset); return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false; } static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl) { u32 sw_reset; Loading Loading @@ -2479,6 +2535,8 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser) .config_dto = dp_catalog_panel_config_dto, .dsc_cfg = dp_catalog_panel_dsc_cfg, .pps_flush = dp_catalog_panel_pps_flush, .dhdr_flush = dp_catalog_panel_dhdr_flush, .dhdr_busy = dp_catalog_panel_dhdr_busy, }; if (!dev || !parser) { Loading drivers/gpu/drm/msm/dp/dp_catalog.h +4 −1 Original line number Diff line number Diff line Loading @@ -217,7 +217,8 @@ struct dp_catalog_panel { struct dp_dsc_cfg_data dsc; int (*timing_cfg)(struct dp_catalog_panel *panel); void (*config_hdr)(struct dp_catalog_panel *panel, bool en); void (*config_hdr)(struct dp_catalog_panel *panel, bool en, u32 dhdr_max_pkts); void (*tpg_config)(struct dp_catalog_panel *panel, bool enable); void (*config_spd)(struct dp_catalog_panel *panel); void (*config_misc)(struct dp_catalog_panel *panel); Loading @@ -228,6 +229,8 @@ struct dp_catalog_panel { void (*config_dto)(struct dp_catalog_panel *panel, bool ack); void (*dsc_cfg)(struct dp_catalog_panel *panel); void (*pps_flush)(struct dp_catalog_panel *panel); void (*dhdr_flush)(struct dp_catalog_panel *panel); bool (*dhdr_busy)(struct dp_catalog_panel *panel); }; struct dp_catalog; Loading drivers/gpu/drm/msm/dp/dp_ctrl.c +1 −0 Original line number Diff line number Diff line Loading @@ -944,6 +944,7 @@ static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl, y_frac_enum = (u32)((temp1 == temp2) ? temp1 : temp1 + 1); panel->mst_target_sc = raw_target_sc; *p_x_int = x_int; *p_y_frac_enum = y_frac_enum; Loading drivers/gpu/drm/msm/dp/dp_debug.c +1 −1 Original line number Diff line number Diff line Loading @@ -1279,7 +1279,7 @@ static ssize_t dp_debug_write_hdr(struct file *file, len = -EINVAL; } debug->panel->setup_hdr(debug->panel, &c_state->hdr_meta); debug->panel->setup_hdr(debug->panel, &c_state->hdr_meta, false, 0); end: return len; } Loading drivers/gpu/drm/msm/dp/dp_display.c +11 −7 Original line number Diff line number Diff line Loading @@ -1497,7 +1497,7 @@ static void dp_display_stream_post_enable(struct dp_display_private *dp, struct dp_panel *dp_panel) { dp_panel->spd_config(dp_panel); dp_panel->setup_hdr(dp_panel, NULL); dp_panel->setup_hdr(dp_panel, NULL, false, 0); } static int dp_display_post_enable(struct dp_display *dp_display, void *panel) Loading Loading @@ -1903,23 +1903,27 @@ static void dp_display_convert_to_dp_mode(struct dp_display *dp_display, } static int dp_display_config_hdr(struct dp_display *dp_display, void *panel, struct drm_msm_ext_hdr_metadata *hdr) struct drm_msm_ext_hdr_metadata *hdr, bool dhdr_update) { int rc = 0; struct dp_display_private *dp; struct dp_panel *dp_panel; struct dp_display_private *dp; u64 core_clk_rate; if (!dp_display || !panel) { pr_err("invalid input\n"); return -EINVAL; } dp = container_of(dp_display, struct dp_display_private, dp_display); dp_panel = panel; dp = container_of(dp_display, struct dp_display_private, dp_display); rc = dp_panel->setup_hdr(dp_panel, hdr); core_clk_rate = dp->power->clk_get_rate(dp->power, "core_clk"); if (!core_clk_rate) { pr_err("invalid rate for core_clk\n"); return -EINVAL; } return rc; return dp_panel->setup_hdr(dp_panel, hdr, dhdr_update, core_clk_rate); } static int dp_display_create_workqueue(struct dp_display_private *dp) Loading Loading
drivers/gpu/drm/msm/dp/dp_catalog.c +62 −4 Original line number Diff line number Diff line Loading @@ -64,6 +64,11 @@ static u8 const vm_voltage_swing[4][4] = { {0xFF, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */ }; enum dp_flush_bit { DP_PPS_FLUSH, DP_DHDR_FLUSH, }; struct dp_catalog_io { struct dp_io_data *dp_ahb; struct dp_io_data *dp_aux; Loading Loading @@ -572,14 +577,16 @@ static void dp_catalog_panel_setup_vsc_sdp(struct dp_catalog_panel *panel) DUMP_PREFIX_NONE, 16, 4, buf, off, false); } static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en, u32 dhdr_max_pkts) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; u32 cfg, cfg2, misc; u32 cfg, cfg2, cfg4, misc; u32 sdp_cfg_off = 0; u32 sdp_cfg2_off = 0; u32 sdp_cfg3_off = 0; u32 sdp_cfg4_off = 0; u32 misc1_misc0_off = 0; if (!panel) { Loading @@ -599,6 +606,7 @@ static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) sdp_cfg_off = MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; sdp_cfg2_off = MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; sdp_cfg3_off = MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; sdp_cfg4_off = MMSS_DP1_SDP_CFG4 - MMSS_DP_SDP_CFG4; misc1_misc0_off = DP1_MISC1_MISC0 - DP_MISC1_MISC0; } Loading @@ -620,6 +628,13 @@ static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2); /* DHDR_EN, DHDR_PACKET_LIMIT */ if (dhdr_max_pkts) { cfg4 = (dhdr_max_pkts << 1) | BIT(0); dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4); } dp_catalog_panel_setup_vsc_sdp(panel); dp_catalog_panel_setup_infoframe_sdp(panel); Loading @@ -641,6 +656,11 @@ static void dp_catalog_panel_config_hdr(struct dp_catalog_panel *panel, bool en) dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG2 + sdp_cfg2_off, cfg2); /* DHDR_EN, DHDR_PACKET_LIMIT */ cfg4 = 0; dp_write(catalog->exe_mode, io_data, MMSS_DP_SDP_CFG4 + sdp_cfg4_off, cfg4); /* switch back to MSA */ misc &= ~BIT(14); Loading Loading @@ -1192,7 +1212,8 @@ static void dp_catalog_panel_dsc_cfg(struct dp_catalog_panel *panel) reg, panel->stream_id); } static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel) static void dp_catalog_panel_dp_flush(struct dp_catalog_panel *panel, enum dp_flush_bit flush_bit) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; Loading @@ -1217,12 +1238,47 @@ static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel) offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH; dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset); dp_flush |= BIT(0); dp_flush |= BIT(flush_bit); dp_write(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset, dp_flush); } static void dp_catalog_panel_pps_flush(struct dp_catalog_panel *panel) { dp_catalog_panel_dp_flush(panel, DP_PPS_FLUSH); pr_debug("pps flush for stream:%d\n", panel->stream_id); } static void dp_catalog_panel_dhdr_flush(struct dp_catalog_panel *panel) { dp_catalog_panel_dp_flush(panel, DP_DHDR_FLUSH); pr_debug("dhdr flush for stream:%d\n", panel->stream_id); } static bool dp_catalog_panel_dhdr_busy(struct dp_catalog_panel *panel) { struct dp_catalog_private *catalog; struct dp_io_data *io_data; u32 dp_flush, offset; if (panel->stream_id >= DP_STREAM_MAX) { pr_err("invalid stream_id:%d\n", panel->stream_id); return false; } catalog = dp_catalog_get_priv(panel); io_data = catalog->io.dp_link; if (panel->stream_id == DP_STREAM_0) offset = 0; else offset = MMSS_DP1_FLUSH - MMSS_DP_FLUSH; dp_flush = dp_read(catalog->exe_mode, io_data, MMSS_DP_FLUSH + offset); return dp_flush & BIT(DP_DHDR_FLUSH) ? true : false; } static void dp_catalog_ctrl_reset(struct dp_catalog_ctrl *ctrl) { u32 sw_reset; Loading Loading @@ -2479,6 +2535,8 @@ struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_parser *parser) .config_dto = dp_catalog_panel_config_dto, .dsc_cfg = dp_catalog_panel_dsc_cfg, .pps_flush = dp_catalog_panel_pps_flush, .dhdr_flush = dp_catalog_panel_dhdr_flush, .dhdr_busy = dp_catalog_panel_dhdr_busy, }; if (!dev || !parser) { Loading
drivers/gpu/drm/msm/dp/dp_catalog.h +4 −1 Original line number Diff line number Diff line Loading @@ -217,7 +217,8 @@ struct dp_catalog_panel { struct dp_dsc_cfg_data dsc; int (*timing_cfg)(struct dp_catalog_panel *panel); void (*config_hdr)(struct dp_catalog_panel *panel, bool en); void (*config_hdr)(struct dp_catalog_panel *panel, bool en, u32 dhdr_max_pkts); void (*tpg_config)(struct dp_catalog_panel *panel, bool enable); void (*config_spd)(struct dp_catalog_panel *panel); void (*config_misc)(struct dp_catalog_panel *panel); Loading @@ -228,6 +229,8 @@ struct dp_catalog_panel { void (*config_dto)(struct dp_catalog_panel *panel, bool ack); void (*dsc_cfg)(struct dp_catalog_panel *panel); void (*pps_flush)(struct dp_catalog_panel *panel); void (*dhdr_flush)(struct dp_catalog_panel *panel); bool (*dhdr_busy)(struct dp_catalog_panel *panel); }; struct dp_catalog; Loading
drivers/gpu/drm/msm/dp/dp_ctrl.c +1 −0 Original line number Diff line number Diff line Loading @@ -944,6 +944,7 @@ static void dp_ctrl_mst_calculate_rg(struct dp_ctrl_private *ctrl, y_frac_enum = (u32)((temp1 == temp2) ? temp1 : temp1 + 1); panel->mst_target_sc = raw_target_sc; *p_x_int = x_int; *p_y_frac_enum = y_frac_enum; Loading
drivers/gpu/drm/msm/dp/dp_debug.c +1 −1 Original line number Diff line number Diff line Loading @@ -1279,7 +1279,7 @@ static ssize_t dp_debug_write_hdr(struct file *file, len = -EINVAL; } debug->panel->setup_hdr(debug->panel, &c_state->hdr_meta); debug->panel->setup_hdr(debug->panel, &c_state->hdr_meta, false, 0); end: return len; } Loading
drivers/gpu/drm/msm/dp/dp_display.c +11 −7 Original line number Diff line number Diff line Loading @@ -1497,7 +1497,7 @@ static void dp_display_stream_post_enable(struct dp_display_private *dp, struct dp_panel *dp_panel) { dp_panel->spd_config(dp_panel); dp_panel->setup_hdr(dp_panel, NULL); dp_panel->setup_hdr(dp_panel, NULL, false, 0); } static int dp_display_post_enable(struct dp_display *dp_display, void *panel) Loading Loading @@ -1903,23 +1903,27 @@ static void dp_display_convert_to_dp_mode(struct dp_display *dp_display, } static int dp_display_config_hdr(struct dp_display *dp_display, void *panel, struct drm_msm_ext_hdr_metadata *hdr) struct drm_msm_ext_hdr_metadata *hdr, bool dhdr_update) { int rc = 0; struct dp_display_private *dp; struct dp_panel *dp_panel; struct dp_display_private *dp; u64 core_clk_rate; if (!dp_display || !panel) { pr_err("invalid input\n"); return -EINVAL; } dp = container_of(dp_display, struct dp_display_private, dp_display); dp_panel = panel; dp = container_of(dp_display, struct dp_display_private, dp_display); rc = dp_panel->setup_hdr(dp_panel, hdr); core_clk_rate = dp->power->clk_get_rate(dp->power, "core_clk"); if (!core_clk_rate) { pr_err("invalid rate for core_clk\n"); return -EINVAL; } return rc; return dp_panel->setup_hdr(dp_panel, hdr, dhdr_update, core_clk_rate); } static int dp_display_create_workqueue(struct dp_display_private *dp) Loading