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Commit 870e0ecc authored by Niklas Cassel's avatar Niklas Cassel Committed by Arnd Bergmann
Browse files

ARM: dts: artpec: add disabled node for PCIe endpoint mode 



The PCIe controller in the artpec6 SoC supports both root complex and
endpoint mode, however, the controller can only be used in one of the
modes.

Both pci nodes are disabled by default. A DTS file can enable one of
them, depending on what mode it wants to run.

Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent e4202ef7

arch/arm/boot/dts/artpec6.dtsi

+18 −0
Original line number Diff line number Diff line
@@ -154,6 +154,10 @@ 
		interrupt-affinity = <&cpu0>, <&cpu1>;

	};



	/*

	 * Both pci nodes cannot be enabled at the same time,

	 * leave the unwanted node as disabled.

	 */

	pcie: pcie@f8050000 {

		compatible = "axis,artpec6-pcie", "snps,dw-pcie";

		reg = <0xf8050000 0x2000
@@ -181,6 +185,20 @@ 
		status = "disabled";

	};



	pcie_ep: pcie_ep@f8050000 {

		compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";

		reg = <0xf8050000 0x2000

		       0xf8051000 0x2000

		       0xf8040000 0x1000

		       0xc0000000 0x20000000>;

		reg-names = "dbi", "dbi2", "phy", "addr_space";

		num-ib-windows = <6>;

		num-ob-windows = <2>;

		num-lanes = <2>;

		axis,syscon-pcie = <&syscon>;

		status = "disabled";

	};



	pinctrl: pinctrl@f801d000 {

		compatible = "axis,artpec6-pinctrl";

		reg = <0xf801d000 0x400>;