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Commit 85fb88d5 authored by Hareesh Gundu's avatar Hareesh Gundu Committed by Archana Sriram
Browse files

msm: kgsl: Add A504 GPU support for SDM429 



Add A504 GPUID and initial settings to support
graphics functionality on SDM429.

Change-Id: I3e967cea59cd8d5eb687ba5701a80689a24c0475
Signed-off-by: default avatarHareesh Gundu <hareeshg@codeaurora.org>
Signed-off-by: default avatarAmit Kushwaha <kushwaha@codeaurora.org>
Signed-off-by: default avatarArchana Sriram <apsrir@codeaurora.org>
parent 3a4cc727

drivers/gpu/msm/adreno-gpulist.h

+18 −0
Original line number Diff line number Diff line
@@ -272,6 +272,23 @@ static const struct adreno_reglist a50x_hwcg_regs[] = { 
	{A5XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}

};



static const struct adreno_a5xx_core adreno_gpu_core_a504 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A504, 5, 0, 4, ANY_ID),

		.features = ADRENO_PREEMPTION | ADRENO_64BIT,

		.gpudev = &adreno_a5xx_gpudev,

		.gmem_size = (SZ_128K + SZ_8K),

		.busy_mask = 0xfffffffe,

		.bus_width = 16,

	},

	.pm4fw_name = "a530_pm4.fw",

	.pfpfw_name = "a530_pfp.fw",

	.hwcg = a50x_hwcg_regs,

	.hwcg_count = ARRAY_SIZE(a50x_hwcg_regs),

	.vbif = a530_vbif_regs,

	.vbif_count = ARRAY_SIZE(a530_vbif_regs),

};



static const struct adreno_a5xx_core adreno_gpu_core_a505 = {

	.base = {

		DEFINE_ADRENO_REV(ADRENO_REV_A505, 5, 0, 5, ANY_ID),
@@ -1498,6 +1515,7 @@ static const struct adreno_gpu_core *adreno_gpulist[] = { 
	&adreno_gpu_core_a540v2.base,

	&adreno_gpu_core_a512.base,

	&adreno_gpu_core_a508.base,

	&adreno_gpu_core_a504.base,

	&adreno_gpu_core_a630v1,	/* Deprecated */

	&adreno_gpu_core_a630v2.base,

	&adreno_gpu_core_a615.base,

drivers/gpu/msm/adreno.h

+5 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2008-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2008-2021, The Linux Foundation. All rights reserved.

 */

#ifndef __ADRENO_H

#define __ADRENO_H
@@ -202,6 +202,7 @@ enum adreno_gpurev { 
	ADRENO_REV_A418 = 418,

	ADRENO_REV_A420 = 420,

	ADRENO_REV_A430 = 430,

	ADRENO_REV_A504 = 504,

	ADRENO_REV_A505 = 505,

	ADRENO_REV_A506 = 506,

	ADRENO_REV_A508 = 508,
@@ -1150,6 +1151,7 @@ static inline int adreno_is_a5xx(struct adreno_device *adreno_dev) 
			ADRENO_GPUREV(adreno_dev) < 600;

}



ADRENO_TARGET(a504, ADRENO_REV_A504)

ADRENO_TARGET(a505, ADRENO_REV_A505)

ADRENO_TARGET(a506, ADRENO_REV_A506)

ADRENO_TARGET(a508, ADRENO_REV_A508)
@@ -1170,9 +1172,9 @@ static inline int adreno_is_a530v3(struct adreno_device *adreno_dev) 
		(ADRENO_CHIPID_PATCH(adreno_dev->chipid) == 2);

}



static inline int adreno_is_a505_or_a506(struct adreno_device *adreno_dev)

static inline int adreno_is_a504_to_a506(struct adreno_device *adreno_dev)

{

	return ADRENO_GPUREV(adreno_dev) >= 505 &&

	return ADRENO_GPUREV(adreno_dev) >= 504 &&

			ADRENO_GPUREV(adreno_dev) <= 506;

}

drivers/gpu/msm/adreno_a5xx.c

+6 −4
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.

 */



#include <linux/clk/qcom.h>
@@ -95,6 +95,7 @@ static const struct { 
} a5xx_efuse_funcs[] = {

	{ adreno_is_a530, a530_efuse_leakage },

	{ adreno_is_a530, a530_efuse_speed_bin },

	{ adreno_is_a504, a530_efuse_speed_bin },

	{ adreno_is_a505, a530_efuse_speed_bin },

	{ adreno_is_a512, a530_efuse_speed_bin },

	{ adreno_is_a508, a530_efuse_speed_bin },
@@ -119,7 +120,7 @@ static void a5xx_platform_setup(struct adreno_device *adreno_dev) 
{

	struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev);



	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {

	if (adreno_is_a504_to_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {

		gpudev->snapshot_data->sect_sizes->cp_meq = 32;

		gpudev->snapshot_data->sect_sizes->cp_merciu = 1024;

		gpudev->snapshot_data->sect_sizes->roq = 256;
@@ -1525,7 +1526,7 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	 * Below CP registers are 0x0 by default, program init

	 * values based on a5xx flavor.

	 */

	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {

	if (adreno_is_a504_to_a506(adreno_dev) || adreno_is_a508(adreno_dev)) {

		kgsl_regwrite(device, A5XX_CP_MEQ_THRESHOLDS, 0x20);

		kgsl_regwrite(device, A5XX_CP_MERCIU_SIZE, 0x400);

		kgsl_regwrite(device, A5XX_CP_ROQ_THRESHOLDS_2, 0x40000030);
@@ -1551,7 +1552,7 @@ static void a5xx_start(struct adreno_device *adreno_dev) 
	 * vtxFifo and primFifo thresholds default values

	 * are different.

	 */

	if (adreno_is_a505_or_a506(adreno_dev) || adreno_is_a508(adreno_dev))

	if (adreno_is_a504_to_a506(adreno_dev) || adreno_is_a508(adreno_dev))

		kgsl_regwrite(device, A5XX_PC_DBG_ECO_CNTL,

						(0x100 << 11 | 0x100 << 22));

	else if (adreno_is_a510(adreno_dev) || adreno_is_a512(adreno_dev))
@@ -1832,6 +1833,7 @@ static int _me_init_ucode_workarounds(struct adreno_device *adreno_dev) 
	switch (ADRENO_GPUREV(adreno_dev)) {

	case ADRENO_REV_A510:

		return 0x00000001; /* Ucode workaround for token end syncs */

	case ADRENO_REV_A504:

	case ADRENO_REV_A505:

	case ADRENO_REV_A506:

	case ADRENO_REV_A530: