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Commit 8594351a authored by Sergio Paracuellos's avatar Sergio Paracuellos Committed by Greg Kroah-Hartman
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staging: mt7621-pci: rename RALINK_PCI_CONFIG_DATA_VIRTUAL_REG definition



RALINK_PCI_CONFIG_DATA_VIRTUAL_REG is a very long name. Make it a bit
shorter renaming it to RALINK_PCI_CONFIG_DATA.

Signed-off-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Tested-by: default avatarNeilBrown <neil@brown.name>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 88e8fa0c
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+4 −4
Original line number Original line Diff line number Diff line
@@ -67,7 +67,7 @@
#define RALINK_PCIE2_CLK_EN		BIT(26)
#define RALINK_PCIE2_CLK_EN		BIT(26)


#define RALINK_PCI_CONFIG_ADDR		0x20
#define RALINK_PCI_CONFIG_ADDR		0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG	0x24
#define RALINK_PCI_CONFIG_DATA		0x24
#define RALINK_PCI_MEMBASE		0x28
#define RALINK_PCI_MEMBASE		0x28
#define RALINK_PCI_IOBASE		0x2C
#define RALINK_PCI_IOBASE		0x2C
#define RALINK_PCIE0_RST		BIT(24)
#define RALINK_PCIE0_RST		BIT(24)
@@ -187,7 +187,7 @@ static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,


	writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
	writel(address, pcie->base + RALINK_PCI_CONFIG_ADDR);


	return pcie->base + RALINK_PCI_CONFIG_DATA_VIRTUAL_REG + (where & 3);
	return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
}
}


struct pci_ops mt7621_pci_ops = {
struct pci_ops mt7621_pci_ops = {
@@ -202,7 +202,7 @@ read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);


	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
}
}


static void
static void
@@ -211,7 +211,7 @@ write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
	u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);


	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA_VIRTUAL_REG);
	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
}


int
int