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Commit 852fde0a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'mediatek-drm-fixes-4.19' of... 

Merge branch 'mediatek-drm-fixes-4.19' of https://github.com/ckhu-mediatek/linux.git-tags

 into drm-fixes

"Here are some fixes for mediatek drm driver."

Mostly fixes around the RDMA and Overlay

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: CK Hu <ck.hu@mediatek.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1535346194.27648.5.camel@mtksdaap41
parents 5b394b2d 08bcbed7

drivers/gpu/drm/mediatek/mtk_disp_ovl.c

+11 −0
Original line number Diff line number Diff line
@@ -132,6 +132,11 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, 
	writel(0x0, comp->regs + DISP_REG_OVL_RST);

}



static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)

{

	return 4;

}



static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)

{

	unsigned int reg;
@@ -157,6 +162,11 @@ static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx) 


static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)

{

	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"

	 * is defined in mediatek HW data sheet.

	 * The alphabet order in XXX is no relation to data

	 * arrangement in memory.

	 */

	switch (fmt) {

	default:

	case DRM_FORMAT_RGB565:
@@ -221,6 +231,7 @@ static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = { 
	.stop = mtk_ovl_stop,

	.enable_vblank = mtk_ovl_enable_vblank,

	.disable_vblank = mtk_ovl_disable_vblank,

	.layer_nr = mtk_ovl_layer_nr,

	.layer_on = mtk_ovl_layer_on,

	.layer_off = mtk_ovl_layer_off,

	.layer_config = mtk_ovl_layer_config,

drivers/gpu/drm/mediatek/mtk_disp_rdma.c

+92 −0
Original line number Diff line number Diff line
@@ -31,14 +31,31 @@ 
#define RDMA_REG_UPDATE_INT				BIT(0)

#define DISP_REG_RDMA_GLOBAL_CON		0x0010

#define RDMA_ENGINE_EN					BIT(0)

#define RDMA_MODE_MEMORY				BIT(1)

#define DISP_REG_RDMA_SIZE_CON_0		0x0014

#define RDMA_MATRIX_ENABLE				BIT(17)

#define RDMA_MATRIX_INT_MTX_SEL				GENMASK(23, 20)

#define RDMA_MATRIX_INT_MTX_BT601_to_RGB		(6 << 20)

#define DISP_REG_RDMA_SIZE_CON_1		0x0018

#define DISP_REG_RDMA_TARGET_LINE		0x001c

#define DISP_RDMA_MEM_CON			0x0024

#define MEM_MODE_INPUT_FORMAT_RGB565			(0x000 << 4)

#define MEM_MODE_INPUT_FORMAT_RGB888			(0x001 << 4)

#define MEM_MODE_INPUT_FORMAT_RGBA8888			(0x002 << 4)

#define MEM_MODE_INPUT_FORMAT_ARGB8888			(0x003 << 4)

#define MEM_MODE_INPUT_FORMAT_UYVY			(0x004 << 4)

#define MEM_MODE_INPUT_FORMAT_YUYV			(0x005 << 4)

#define MEM_MODE_INPUT_SWAP				BIT(8)

#define DISP_RDMA_MEM_SRC_PITCH			0x002c

#define DISP_RDMA_MEM_GMC_SETTING_0		0x0030

#define DISP_REG_RDMA_FIFO_CON			0x0040

#define RDMA_FIFO_UNDERFLOW_EN				BIT(31)

#define RDMA_FIFO_PSEUDO_SIZE(bytes)			(((bytes) / 16) << 16)

#define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)		((bytes) / 16)

#define RDMA_FIFO_SIZE(rdma)			((rdma)->data->fifo_size)

#define DISP_RDMA_MEM_START_ADDR		0x0f00



#define RDMA_MEM_GMC				0x40402020



struct mtk_disp_rdma_data {

	unsigned int fifo_size;
@@ -138,12 +155,87 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, 
	writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);

}



static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,

				     unsigned int fmt)

{

	/* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"

	 * is defined in mediatek HW data sheet.

	 * The alphabet order in XXX is no relation to data

	 * arrangement in memory.

	 */

	switch (fmt) {

	default:

	case DRM_FORMAT_RGB565:

		return MEM_MODE_INPUT_FORMAT_RGB565;

	case DRM_FORMAT_BGR565:

		return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;

	case DRM_FORMAT_RGB888:

		return MEM_MODE_INPUT_FORMAT_RGB888;

	case DRM_FORMAT_BGR888:

		return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;

	case DRM_FORMAT_RGBX8888:

	case DRM_FORMAT_RGBA8888:

		return MEM_MODE_INPUT_FORMAT_ARGB8888;

	case DRM_FORMAT_BGRX8888:

	case DRM_FORMAT_BGRA8888:

		return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;

	case DRM_FORMAT_XRGB8888:

	case DRM_FORMAT_ARGB8888:

		return MEM_MODE_INPUT_FORMAT_RGBA8888;

	case DRM_FORMAT_XBGR8888:

	case DRM_FORMAT_ABGR8888:

		return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;

	case DRM_FORMAT_UYVY:

		return MEM_MODE_INPUT_FORMAT_UYVY;

	case DRM_FORMAT_YUYV:

		return MEM_MODE_INPUT_FORMAT_YUYV;

	}

}



static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)

{

	return 1;

}



static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,

				  struct mtk_plane_state *state)

{

	struct mtk_disp_rdma *rdma = comp_to_rdma(comp);

	struct mtk_plane_pending_state *pending = &state->pending;

	unsigned int addr = pending->addr;

	unsigned int pitch = pending->pitch & 0xffff;

	unsigned int fmt = pending->format;

	unsigned int con;



	con = rdma_fmt_convert(rdma, fmt);

	writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);



	if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {

		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,

				 RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);

		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,

				 RDMA_MATRIX_INT_MTX_SEL,

				 RDMA_MATRIX_INT_MTX_BT601_to_RGB);

	} else {

		rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,

				 RDMA_MATRIX_ENABLE, 0);

	}



	writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);

	writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);

	writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);

	rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,

			 RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);

}



static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {

	.config = mtk_rdma_config,

	.start = mtk_rdma_start,

	.stop = mtk_rdma_stop,

	.enable_vblank = mtk_rdma_enable_vblank,

	.disable_vblank = mtk_rdma_disable_vblank,

	.layer_nr = mtk_rdma_layer_nr,

	.layer_config = mtk_rdma_layer_config,

};



static int mtk_disp_rdma_bind(struct device *dev, struct device *master,

drivers/gpu/drm/mediatek/mtk_drm_crtc.c

+27 −20
Original line number Diff line number Diff line
@@ -45,7 +45,8 @@ struct mtk_drm_crtc { 
	bool				pending_needs_vblank;

	struct drm_pending_vblank_event	*event;



	struct drm_plane		planes[OVL_LAYER_NR];

	struct drm_plane		*planes;

	unsigned int			layer_nr;

	bool				pending_planes;



	void __iomem			*config_regs;
@@ -171,9 +172,9 @@ static void mtk_drm_crtc_mode_set_nofb(struct drm_crtc *crtc) 
static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];

	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];



	mtk_ddp_comp_enable_vblank(ovl, &mtk_crtc->base);

	mtk_ddp_comp_enable_vblank(comp, &mtk_crtc->base);



	return 0;

}
@@ -181,9 +182,9 @@ static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) 
static void mtk_drm_crtc_disable_vblank(struct drm_crtc *crtc)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];

	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];



	mtk_ddp_comp_disable_vblank(ovl);

	mtk_ddp_comp_disable_vblank(comp);

}



static int mtk_crtc_ddp_clk_enable(struct mtk_drm_crtc *mtk_crtc)
@@ -286,7 +287,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) 
	}



	/* Initially configure all planes */

	for (i = 0; i < OVL_LAYER_NR; i++) {

	for (i = 0; i < mtk_crtc->layer_nr; i++) {

		struct drm_plane *plane = &mtk_crtc->planes[i];

		struct mtk_plane_state *plane_state;
@@ -334,7 +335,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 
{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);

	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];

	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];

	unsigned int i;



	/*
@@ -343,7 +344,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 
	 * queue update module registers on vblank.

	 */

	if (state->pending_config) {

		mtk_ddp_comp_config(ovl, state->pending_width,

		mtk_ddp_comp_config(comp, state->pending_width,

				    state->pending_height,

				    state->pending_vrefresh, 0);
@@ -351,14 +352,14 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc) 
	}



	if (mtk_crtc->pending_planes) {

		for (i = 0; i < OVL_LAYER_NR; i++) {

		for (i = 0; i < mtk_crtc->layer_nr; i++) {

			struct drm_plane *plane = &mtk_crtc->planes[i];

			struct mtk_plane_state *plane_state;



			plane_state = to_mtk_plane_state(plane->state);



			if (plane_state->pending.config) {

				mtk_ddp_comp_layer_config(ovl, i, plane_state);

				mtk_ddp_comp_layer_config(comp, i, plane_state);

				plane_state->pending.config = false;

			}

		}
@@ -370,12 +371,12 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 
				       struct drm_crtc_state *old_state)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];

	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];

	int ret;



	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);



	ret = mtk_smi_larb_get(ovl->larb_dev);

	ret = mtk_smi_larb_get(comp->larb_dev);

	if (ret) {

		DRM_ERROR("Failed to get larb: %d\n", ret);

		return;
@@ -383,7 +384,7 @@ static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc, 


	ret = mtk_crtc_ddp_hw_init(mtk_crtc);

	if (ret) {

		mtk_smi_larb_put(ovl->larb_dev);

		mtk_smi_larb_put(comp->larb_dev);

		return;

	}
@@ -395,7 +396,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 
					struct drm_crtc_state *old_state)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_ddp_comp *ovl = mtk_crtc->ddp_comp[0];

	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];

	int i;



	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
@@ -403,7 +404,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 
		return;



	/* Set all pending plane state to disabled */

	for (i = 0; i < OVL_LAYER_NR; i++) {

	for (i = 0; i < mtk_crtc->layer_nr; i++) {

		struct drm_plane *plane = &mtk_crtc->planes[i];

		struct mtk_plane_state *plane_state;
@@ -418,7 +419,7 @@ static void mtk_drm_crtc_atomic_disable(struct drm_crtc *crtc, 


	drm_crtc_vblank_off(crtc);

	mtk_crtc_ddp_hw_fini(mtk_crtc);

	mtk_smi_larb_put(ovl->larb_dev);

	mtk_smi_larb_put(comp->larb_dev);



	mtk_crtc->enabled = false;

}
@@ -450,7 +451,7 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc, 


	if (mtk_crtc->event)

		mtk_crtc->pending_needs_vblank = true;

	for (i = 0; i < OVL_LAYER_NR; i++) {

	for (i = 0; i < mtk_crtc->layer_nr; i++) {

		struct drm_plane *plane = &mtk_crtc->planes[i];

		struct mtk_plane_state *plane_state;
@@ -516,7 +517,7 @@ static int mtk_drm_crtc_init(struct drm_device *drm, 
	return ret;

}



void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl)

void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)

{

	struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);

	struct mtk_drm_private *priv = crtc->dev->dev_private;
@@ -598,7 +599,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
		mtk_crtc->ddp_comp[i] = comp;

	}



	for (zpos = 0; zpos < OVL_LAYER_NR; zpos++) {

	mtk_crtc->layer_nr = mtk_ddp_comp_layer_nr(mtk_crtc->ddp_comp[0]);

	mtk_crtc->planes = devm_kzalloc(dev, mtk_crtc->layer_nr *

					sizeof(struct drm_plane),

					GFP_KERNEL);



	for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {

		type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :

				(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :

						DRM_PLANE_TYPE_OVERLAY;
@@ -609,7 +615,8 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, 
	}



	ret = mtk_drm_crtc_init(drm_dev, mtk_crtc, &mtk_crtc->planes[0],

				&mtk_crtc->planes[1], pipe);

				mtk_crtc->layer_nr > 1 ? &mtk_crtc->planes[1] :

				NULL, pipe);

	if (ret < 0)

		goto unprepare;

	drm_mode_crtc_set_gamma_size(&mtk_crtc->base, MTK_LUT_SIZE);

drivers/gpu/drm/mediatek/mtk_drm_crtc.h

+1 −2
Original line number Diff line number Diff line
@@ -18,13 +18,12 @@ 
#include "mtk_drm_ddp_comp.h"

#include "mtk_drm_plane.h"



#define OVL_LAYER_NR	4

#define MTK_LUT_SIZE	512

#define MTK_MAX_BPC	10

#define MTK_MIN_BPC	3



void mtk_drm_crtc_commit(struct drm_crtc *crtc);

void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *ovl);

void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp);

int mtk_drm_crtc_create(struct drm_device *drm_dev,

			const enum mtk_ddp_comp_id *path,

			unsigned int path_len);

drivers/gpu/drm/mediatek/mtk_drm_ddp.c

+17 −1
Original line number Diff line number Diff line
@@ -106,6 +106,8 @@ 
#define OVL1_MOUT_EN_COLOR1		0x1

#define GAMMA_MOUT_EN_RDMA1		0x1

#define RDMA0_SOUT_DPI0			0x2

#define RDMA0_SOUT_DPI1			0x3

#define RDMA0_SOUT_DSI1			0x1

#define RDMA0_SOUT_DSI2			0x4

#define RDMA0_SOUT_DSI3			0x5

#define RDMA1_SOUT_DPI0			0x2
@@ -122,6 +124,8 @@ 
#define DPI0_SEL_IN_RDMA2		0x3

#define DPI1_SEL_IN_RDMA1		(0x1 << 8)

#define DPI1_SEL_IN_RDMA2		(0x3 << 8)

#define DSI0_SEL_IN_RDMA1		0x1

#define DSI0_SEL_IN_RDMA2		0x4

#define DSI1_SEL_IN_RDMA1		0x1

#define DSI1_SEL_IN_RDMA2		0x4

#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
@@ -224,6 +228,12 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur, 
	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {

		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;

		value = RDMA0_SOUT_DPI0;

	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {

		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;

		value = RDMA0_SOUT_DPI1;

	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {

		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;

		value = RDMA0_SOUT_DSI1;

	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {

		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;

		value = RDMA0_SOUT_DSI2;
@@ -282,6 +292,9 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, 
	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {

		*addr = DISP_REG_CONFIG_DPI_SEL_IN;

		value = DPI1_SEL_IN_RDMA1;

	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {

		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;

		value = DSI0_SEL_IN_RDMA1;

	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {

		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;

		value = DSI1_SEL_IN_RDMA1;
@@ -297,8 +310,11 @@ static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur, 
	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {

		*addr = DISP_REG_CONFIG_DPI_SEL_IN;

		value = DPI1_SEL_IN_RDMA2;

	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {

	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {

		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;

		value = DSI0_SEL_IN_RDMA2;

	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {

		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;

		value = DSI1_SEL_IN_RDMA2;

	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {

		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;