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Commit 852663d9 authored by Pawel Moll's avatar Pawel Moll
Browse files

ARM: vexpress: Make the debug UART detection more specific 



Base the UART detection heuristic on architecturally defined
MIDR register instead of implementation dependent CBAR. The
only tile using the original memory map is V2P-CA9 with Cortex
A9 r0p1, which MIDR contains value 0x410fc091.

Signed-off-by: default avatarPawel Moll <pawel.moll@arm.com>
parent ddffeb8c

arch/arm/include/debug/vexpress.S

+6 −4
Original line number Diff line number Diff line
@@ -23,12 +23,14 @@ 
		.macro	addruart,rp,rv,tmp



		@ Make an educated guess regarding the memory map:

		@ - the original A9 core tile, which has MPCore peripherals

		@   located at 0x1e000000, should use UART at 0x10009000

		@ - the original A9 core tile (based on ARM Cortex-A9 r0p1)

		@   should use UART at 0x10009000

		@ - all other (RS1 complaint) tiles use UART mapped

		@   at 0x1c090000

		mrc	p15, 4, \tmp, c15, c0, 0

		cmp	\tmp, #0x1e000000

		mrc	p15, 0, \rp, c0, c0, 0

		movw	\rv, #0xc091

		movt	\rv, #0x410f

		cmp	\rp, \rv



		@ Original memory map

		moveq	\rp, #DEBUG_LL_UART_OFFSET