Commit 84f2b9b2 authored Feb 02, 2012 by Stephane Eranian Committed by Ingo Molnar Feb 03, 2012

perf: Remove deprecated WARN_ON_ONCE()



With the new throttling/unthrottling code introduced with
commit:

  e050e3f0 ("perf: Fix broken interrupt rate throttling")

we occasionally hit two WARN_ON_ONCE() checks in:

  - intel_pmu_pebs_enable()
  - intel_pmu_lbr_enable()
  - x86_pmu_start()

The assertions are no longer problematic. There is a valid
path where they can trigger but it is harmless.

The assertion can be triggered with:

  $ perf record -e instructions:pp ....

Leading to paths:

  intel_pmu_pebs_enable
  intel_pmu_enable_event
  x86_perf_event_set_period
  x86_pmu_start
  perf_adjust_freq_unthr_context
  perf_event_task_tick
  scheduler_tick

And:

  intel_pmu_lbr_enable
  intel_pmu_enable_event
  x86_perf_event_set_period
  x86_pmu_start
  perf_adjust_freq_unthr_context.
  perf_event_task_tick
  scheduler_tick

cpuc->enabled is always on because when we get to
perf_adjust_freq_unthr_context() the PMU is not totally
disabled. Furthermore when we need to adjust a period,
we only stop the event we need to change and not the
entire PMU. Thus, when we re-enable, cpuc->enabled is
already set. Note that when we stop the event, both
pebs and lbr are stopped if necessary (and possible).

Signed-off-by: Stephane Eranian <eranian@google.com>
Cc: peterz@infradead.org
Link: http://lkml.kernel.org/r/20120202110401.GA30911@quad


Signed-off-by: Ingo Molnar <mingo@elte.hu>

parent 6c073a7e

arch/x86/kernel/cpu/perf_event.c

+0 −3

Original line number	Diff line number	Diff line
		@@ -986,9 +986,6 @@ static void x86_pmu_start(struct perf_event *event, int flags)
		struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
		int idx = event->hw.idx;

		if (WARN_ON_ONCE(!(event->hw.state & PERF_HES_STOPPED)))
		return;

		if (WARN_ON_ONCE(idx == -1))
		return;

arch/x86/kernel/cpu/perf_event_intel_ds.c

+0 −1

Original line number	Diff line number	Diff line
		@@ -439,7 +439,6 @@ void intel_pmu_pebs_enable(struct perf_event *event)
		hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;

		cpuc->pebs_enabled \|= 1ULL << hwc->idx;
		WARN_ON_ONCE(cpuc->enabled);

		if (x86_pmu.intel_cap.pebs_trap && event->attr.precise_ip > 1)
		intel_pmu_lbr_enable(event);

arch/x86/kernel/cpu/perf_event_intel_lbr.c

+0 −2

Original line number	Diff line number	Diff line
		@@ -72,8 +72,6 @@ void intel_pmu_lbr_enable(struct perf_event *event)
		if (!x86_pmu.lbr_nr)
		return;

		WARN_ON_ONCE(cpuc->enabled);

		/*
		* Reset the LBR stack if we changed task context to
		* avoid data leaks.