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Commit 84d43463 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: ACG frequency added in PPTable 



Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent f0694d3b

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_hwmgr.c

+8 −3
Original line number Diff line number Diff line
@@ -1558,7 +1558,8 @@ static int vega10_populate_smc_link_levels(struct pp_hwmgr *hwmgr) 
*/



static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr,

		uint32_t gfx_clock, PllSetting_t *current_gfxclk_level)

		uint32_t gfx_clock, PllSetting_t *current_gfxclk_level,

		uint32_t *acg_freq)

{

	struct phm_ppt_v2_information *table_info =

			(struct phm_ppt_v2_information *)(hwmgr->pptable);
@@ -1609,6 +1610,8 @@ static int vega10_populate_single_gfx_level(struct pp_hwmgr *hwmgr, 
			cpu_to_le16(dividers.usPll_ss_slew_frac);

	current_gfxclk_level->Did = (uint8_t)(dividers.ulDid);



	*acg_freq = gfx_clock / 100; /* 100 Khz to Mhz conversion */



	return 0;

}
@@ -1689,7 +1692,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 
	for (i = 0; i < dpm_table->count; i++) {

		result = vega10_populate_single_gfx_level(hwmgr,

				dpm_table->dpm_levels[i].value,

				&(pp_table->GfxclkLevel[i]));

				&(pp_table->GfxclkLevel[i]),

				&(pp_table->AcgFreqTable[i]));

		if (result)

			return result;

	}
@@ -1698,7 +1702,8 @@ static int vega10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) 
	while (i < NUM_GFXCLK_DPM_LEVELS) {

		result = vega10_populate_single_gfx_level(hwmgr,

				dpm_table->dpm_levels[j].value,

				&(pp_table->GfxclkLevel[i]));

				&(pp_table->GfxclkLevel[i]),

				&(pp_table->AcgFreqTable[i]));

		if (result)

			return result;

		i++;

drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h

+4 −2
Original line number Diff line number Diff line
@@ -315,10 +315,12 @@ typedef struct { 
  uint8_t      AcgEnable[NUM_GFXCLK_DPM_LEVELS];

  GbVdroopTable_t AcgBtcGbVdroopTable;

  QuadraticInt_t  AcgAvfsGb;

  uint32_t     Reserved[4];



  /* ACG Frequency Table, in Mhz */

  uint32_t     AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];



  /* Padding - ignore */

  uint32_t     MmHubPadding[7]; /* SMU internal use */

  uint32_t     MmHubPadding[3]; /* SMU internal use */



} PPTable_t;