fw-api: Add HW header files for QCA5018 (84c021cf) · Commits · e / devices / android_kernel_oneplus_sm7250

hw/qca5018/HALcomdef.h

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		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/

		#ifndef HAL_COMDEF_H
		#define HAL_COMDEF_H
		/*
		==============================================================================

		FILE: HALcomdef.h

		DESCRIPTION:

		==============================================================================

		Edit History

		$Header: //depot/prj/qca/lithium3/wcss/maple_verif/native/register/include/HALcomdef.h#1 $

		when who what, where, why
		-------- --- -----------------------------------------------------------
		06/17/10 sc Included com_dtypes.h and cleaned up typedefs
		05/15/08 gfr Added HAL_ENUM_32BITS macro.
		02/14/08 gfr Added bool32 type.
		11/13/07 gfr Removed dependency on comdef.h
		01/08/07 hxw Created

		==============================================================================
		*/


		/*
		* Assembly wrapper
		*/
		#ifndef _ARM_ASM_

		/*
		* C++ wrapper
		*/
		#ifdef __cplusplus
		extern "C" {
		#endif

		#include "com_dtypes.h"

		/* -----------------------------------------------------------------------
		** Types
		** ----------------------------------------------------------------------- */

		/*
		* Standard integer types.
		*
		* bool32 - boolean, 32 bit (TRUE or FALSE)
		*/
		#ifndef _BOOL32_DEFINED
		typedef unsigned long int bool32;
		#define _BOOL32_DEFINED
		#endif

		/*
		* Macro to allow forcing an enum to 32 bits. The argument should be
		* an identifier in the namespace of the enumeration in question, i.e.
		* for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx).
		*/
		#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF

		/*===========================================================================

		FUNCTION inp, outp, inpw, outpw, inpdw, outpdw

		DESCRIPTION
		IN/OUT port macros for byte and word ports, typically inlined by compilers
		which support these routines

		PARAMETERS
		inp( xx_addr )
		inpw( xx_addr )
		inpdw( xx_addr )
		outp( xx_addr, xx_byte_val )
		outpw( xx_addr, xx_word_val )
		outpdw( xx_addr, xx_dword_val )
		xx_addr - Address of port to read or write (may be memory mapped)
		xx_byte_val - 8 bit value to write
		xx_word_val - 16 bit value to write
		xx_dword_val - 32 bit value to write

		DEPENDENCIES
		None

		RETURN VALUE
		inp/inpw/inpdw: the byte, word or dword read from the given address
		outp/outpw/outpdw: the byte, word or dword written to the given address

		SIDE EFFECTS
		None.

		===========================================================================*/

		/* ARM based targets use memory mapped i/o, so the inp/outp calls are
		** macroized to access memory directly
		*/

		#if defined(VV_FEATURE_COMPILING_64BIT)
		#define inp(port) (((volatile dword ) (port)))
		#define inpw(port) (((volatile word ) (port)))
		#define inpdw(port) (((volatile dword )(port)))

		#define outp(port, val) (((volatile dword ) (port)) = ((dword) (val)))
		#define outpw(port, val) (((volatile word ) (port)) = ((word) (val)))
		#define outpdw(port, val) (((volatile dword ) (port)) = ((dword) (val)))
		#endif
		#ifdef __cplusplus
		}
		#endif

		#endif /* !_ARM_ASM_ */

		#endif /* HAL_COMDEF_H */

hw/qca5018/HALhwio.h

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File added.

Preview size limit exceeded, changes collapsed.

hw/qca5018/buffer_addr_info.h

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		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/

		#ifndef _BUFFER_ADDR_INFO_H_
		#define _BUFFER_ADDR_INFO_H_
		#if !defined(__ASSEMBLER__)
		#endif


		// ################ START SUMMARY #################
		//
		// Dword Fields
		// 0 buffer_addr_31_0[31:0]
		// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11]
		//
		// ################ END SUMMARY #################

		#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2

		struct buffer_addr_info {
		uint32_t buffer_addr_31_0 : 32; //[31:0]
		uint32_t buffer_addr_39_32 : 8, //[7:0]
		return_buffer_manager : 3, //[10:8]
		sw_buffer_cookie : 21; //[31:11]
		};

		/*

		buffer_addr_31_0

		Address (lower 32 bits) of the MSDU buffer OR
		MSDU_EXTENSION descriptor OR Link Descriptor



		In case of 'NULL' pointer, this field is set to 0

		<legal all>

		buffer_addr_39_32

		Address (upper 8 bits) of the MSDU buffer OR
		MSDU_EXTENSION descriptor OR Link Descriptor



		In case of 'NULL' pointer, this field is set to 0

		<legal all>

		return_buffer_manager

		Consumer: WBM

		Producer: SW/FW



		In case of 'NULL' pointer, this field is set to 0



		Indicates to which buffer manager the buffer OR
		MSDU_EXTENSION descriptor OR link descriptor that is being
		pointed to shall be returned after the frame has been
		processed. It is used by WBM for routing purposes.



		<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
		to the WMB buffer idle list

		<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
		returned to the WMB idle link descriptor idle list

		<enum 2 FW_BM> This buffer shall be returned to the FW

		<enum 3 SW0_BM> This buffer shall be returned to the SW,
		ring 0

		<enum 4 SW1_BM> This buffer shall be returned to the SW,
		ring 1

		<enum 5 SW2_BM> This buffer shall be returned to the SW,
		ring 2

		<enum 6 SW3_BM> This buffer shall be returned to the SW,
		ring 3

		<enum 7 SW4_BM> This buffer shall be returned to the SW,
		ring 4



		<legal all>

		sw_buffer_cookie

		Cookie field exclusively used by SW.



		In case of 'NULL' pointer, this field is set to 0



		HW ignores the contents, accept that it passes the
		programmed value on to other descriptors together with the
		physical address



		Field can be used by SW to for example associate the
		buffers physical address with the virtual address

		The bit definitions as used by SW are within SW HLD
		specification



		NOTE1:

		The three most significant bits can have a special
		meaning in case this struct is embedded in a TX_MPDU_DETAILS
		STRUCT, and field transmit_bw_restriction is set



		In case of NON punctured transmission:

		Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only

		Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only

		Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only

		Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only



		In case of punctured transmission:

		Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only

		Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only

		Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only

		Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only

		Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only

		Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only

		Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only

		Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only



		Note: a punctured transmission is indicated by the
		presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
		TLV



		NOTE 2:The five most significant bits can have a special
		meaning in case this struct is embedded in an
		RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
		configured for passing on the additional info
		from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
		(FR56821). This is not supported in HastingsPrime, Pine or
		Moselle.



		Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
		control field



		Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
		indicates MPDUs with a QoS control field.





		<legal all>
		*/


		/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0

		Address (lower 32 bits) of the MSDU buffer OR
		MSDU_EXTENSION descriptor OR Link Descriptor



		In case of 'NULL' pointer, this field is set to 0

		<legal all>
		*/
		#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000
		#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0
		#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff

		/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32

		Address (upper 8 bits) of the MSDU buffer OR
		MSDU_EXTENSION descriptor OR Link Descriptor



		In case of 'NULL' pointer, this field is set to 0

		<legal all>
		*/
		#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004
		#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0
		#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff

		/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER

		Consumer: WBM

		Producer: SW/FW



		In case of 'NULL' pointer, this field is set to 0



		Indicates to which buffer manager the buffer OR
		MSDU_EXTENSION descriptor OR link descriptor that is being
		pointed to shall be returned after the frame has been
		processed. It is used by WBM for routing purposes.



		<enum 0 WBM_IDLE_BUF_LIST> This buffer shall be returned
		to the WMB buffer idle list

		<enum 1 WBM_IDLE_DESC_LIST> This buffer shall be
		returned to the WMB idle link descriptor idle list

		<enum 2 FW_BM> This buffer shall be returned to the FW

		<enum 3 SW0_BM> This buffer shall be returned to the SW,
		ring 0

		<enum 4 SW1_BM> This buffer shall be returned to the SW,
		ring 1

		<enum 5 SW2_BM> This buffer shall be returned to the SW,
		ring 2

		<enum 6 SW3_BM> This buffer shall be returned to the SW,
		ring 3

		<enum 7 SW4_BM> This buffer shall be returned to the SW,
		ring 4



		<legal all>
		*/
		#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
		#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8
		#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700

		/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE

		Cookie field exclusively used by SW.



		In case of 'NULL' pointer, this field is set to 0



		HW ignores the contents, accept that it passes the
		programmed value on to other descriptors together with the
		physical address



		Field can be used by SW to for example associate the
		buffers physical address with the virtual address

		The bit definitions as used by SW are within SW HLD
		specification



		NOTE1:

		The three most significant bits can have a special
		meaning in case this struct is embedded in a TX_MPDU_DETAILS
		STRUCT, and field transmit_bw_restriction is set



		In case of NON punctured transmission:

		Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only

		Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only

		Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only

		Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only



		In case of punctured transmission:

		Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only

		Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only

		Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only

		Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only

		Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only

		Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only

		Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only

		Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only



		Note: a punctured transmission is indicated by the
		presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler
		TLV



		NOTE 2:The five most significant bits can have a special
		meaning in case this struct is embedded in an
		RX_MSDU_DETAILS STRUCT, and Maple/Spruce Rx DMA is
		configured for passing on the additional info
		from 'RX_MPDU_INFO' structure in 'RX_MPDU_START' TLV
		(FR56821). This is not supported in HastingsPrime, Pine or
		Moselle.



		Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS
		control field



		Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field
		indicates MPDUs with a QoS control field.





		<legal all>
		*/
		#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004
		#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11
		#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800


		#endif // _BUFFER_ADDR_INFO_H_

hw/qca5018/ce_src_desc.h

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		/*
		* Copyright (c) 2020, The Linux Foundation. All rights reserved.
		*
		* Permission to use, copy, modify, and/or distribute this software for any
		* purpose with or without fee is hereby granted, provided that the above
		* copyright notice and this permission notice appear in all copies.
		*
		* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
		* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
		* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
		* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
		* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
		* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
		* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
		*/

		#ifndef _CE_SRC_DESC_H_
		#define _CE_SRC_DESC_H_
		#if !defined(__ASSEMBLER__)
		#endif


		// ################ START SUMMARY #################
		//
		// Dword Fields
		// 0 src_buffer_low[31:0]
		// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16]
		// 2 fw_metadata[15:0], ce_res_1[31:16]
		// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28]
		//
		// ################ END SUMMARY #################

		#define NUM_OF_DWORDS_CE_SRC_DESC 4

		struct ce_src_desc {
		uint32_t src_buffer_low : 32; //[31:0]
		uint32_t src_buffer_high : 8, //[7:0]
		toeplitz_en : 1, //[8]
		src_swap : 1, //[9]
		dest_swap : 1, //[10]
		gather : 1, //[11]
		ce_res_0 : 4, //[15:12]
		length : 16; //[31:16]
		uint32_t fw_metadata : 16, //[15:0]
		ce_res_1 : 16; //[31:16]
		uint32_t ce_res_2 : 20, //[19:0]
		ring_id : 8, //[27:20]
		looping_count : 4; //[31:28]
		};

		/*

		src_buffer_low

		LSB 32 bits of the 40 Bit Pointer to the source buffer

		<legal all>

		src_buffer_high

		MSB 8 bits of the 40 Bit Pointer to the source buffer

		<legal all>

		toeplitz_en

		Enable generation of 32-bit Toeplitz-LFSR hash for the
		data transfer

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>

		src_swap

		Treats source memory organization as big-endian. For
		each dword read (4 bytes), the byte 0 is swapped with byte 3
		and byte 1 is swapped with byte 2.

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>

		dest_swap

		Treats destination memory organization as big-endian.
		For each dword write (4 bytes), the byte 0 is swapped with
		byte 3 and byte 1 is swapped with byte 2.

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>

		gather

		Enables gather of multiple copy engine source
		descriptors to one destination.

		<legal all>

		ce_res_0

		Reserved

		<legal all>

		length

		Length of the buffer in units of octets of the current
		descriptor

		<legal all>

		fw_metadata

		Meta data used by FW

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>

		ce_res_1

		Reserved

		<legal all>

		ce_res_2

		Reserved

		<legal all>

		ring_id

		The buffer pointer ring ID.

		0 refers to the IDLE ring

		1 - N refers to other rings



		Helps with debugging when dumping ring contents.

		<legal all>

		looping_count

		A count value that indicates the number of times the
		producer of entries into the Ring has looped around the
		ring.

		At initialization time, this value is set to 0. On the
		first loop, this value is set to 1. After the max value is
		reached allowed by the number of bits for this field, the
		count value continues with 0 again.

		In case SW is the consumer of the ring entries, it can
		use this field to figure out up to where the producer of
		entries has created new entries. This eliminates the need to
		check where the head pointer' of the ring is located once
		the SW starts processing an interrupt indicating that new
		entries have been put into this ring...

		Also note that SW if it wants only needs to look at the
		LSB bit of this count value.

		<legal all>
		*/


		/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW

		LSB 32 bits of the 40 Bit Pointer to the source buffer

		<legal all>
		*/
		#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000
		#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0
		#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff

		/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH

		MSB 8 bits of the 40 Bit Pointer to the source buffer

		<legal all>
		*/
		#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004
		#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0
		#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff

		/* Description CE_SRC_DESC_1_TOEPLITZ_EN

		Enable generation of 32-bit Toeplitz-LFSR hash for the
		data transfer

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>
		*/
		#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004
		#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8
		#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100

		/* Description CE_SRC_DESC_1_SRC_SWAP

		Treats source memory organization as big-endian. For
		each dword read (4 bytes), the byte 0 is swapped with byte 3
		and byte 1 is swapped with byte 2.

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>
		*/
		#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004
		#define CE_SRC_DESC_1_SRC_SWAP_LSB 9
		#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200

		/* Description CE_SRC_DESC_1_DEST_SWAP

		Treats destination memory organization as big-endian.
		For each dword write (4 bytes), the byte 0 is swapped with
		byte 3 and byte 1 is swapped with byte 2.

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>
		*/
		#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004
		#define CE_SRC_DESC_1_DEST_SWAP_LSB 10
		#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400

		/* Description CE_SRC_DESC_1_GATHER

		Enables gather of multiple copy engine source
		descriptors to one destination.

		<legal all>
		*/
		#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004
		#define CE_SRC_DESC_1_GATHER_LSB 11
		#define CE_SRC_DESC_1_GATHER_MASK 0x00000800

		/* Description CE_SRC_DESC_1_CE_RES_0

		Reserved

		<legal all>
		*/
		#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004
		#define CE_SRC_DESC_1_CE_RES_0_LSB 12
		#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000

		/* Description CE_SRC_DESC_1_LENGTH

		Length of the buffer in units of octets of the current
		descriptor

		<legal all>
		*/
		#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004
		#define CE_SRC_DESC_1_LENGTH_LSB 16
		#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000

		/* Description CE_SRC_DESC_2_FW_METADATA

		Meta data used by FW

		In case of gather field in first source ring entry of
		the gather copy cycle in taken into account.

		<legal all>
		*/
		#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008
		#define CE_SRC_DESC_2_FW_METADATA_LSB 0
		#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff

		/* Description CE_SRC_DESC_2_CE_RES_1

		Reserved

		<legal all>
		*/
		#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008
		#define CE_SRC_DESC_2_CE_RES_1_LSB 16
		#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000

		/* Description CE_SRC_DESC_3_CE_RES_2

		Reserved

		<legal all>
		*/
		#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c
		#define CE_SRC_DESC_3_CE_RES_2_LSB 0
		#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff

		/* Description CE_SRC_DESC_3_RING_ID

		The buffer pointer ring ID.

		0 refers to the IDLE ring

		1 - N refers to other rings



		Helps with debugging when dumping ring contents.

		<legal all>
		*/
		#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c
		#define CE_SRC_DESC_3_RING_ID_LSB 20
		#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000

		/* Description CE_SRC_DESC_3_LOOPING_COUNT

		A count value that indicates the number of times the
		producer of entries into the Ring has looped around the
		ring.

		At initialization time, this value is set to 0. On the
		first loop, this value is set to 1. After the max value is
		reached allowed by the number of bits for this field, the
		count value continues with 0 again.

		In case SW is the consumer of the ring entries, it can
		use this field to figure out up to where the producer of
		entries has created new entries. This eliminates the need to
		check where the head pointer' of the ring is located once
		the SW starts processing an interrupt indicating that new
		entries have been put into this ring...

		Also note that SW if it wants only needs to look at the
		LSB bit of this count value.

		<legal all>
		*/
		#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c
		#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28
		#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000


		#endif // _CE_SRC_DESC_H_

hw/qca5018/ce_stat_desc.h

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