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Commit 842f57ba authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
Browse files

Merge tag 'for-3.19' of... 

Merge tag 'for-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-testing

Kishon writes:

Improvements in phy-core specifically on PHY core finds the PHY in the case
of non-dt boot. Adds three new PHY drivers using the PHY framework and some
miscellaneous fixes and cleanups.
parents fc625960 eee47538

Documentation/devicetree/bindings/ata/marvell.txt

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@@ -6,11 +6,17 @@ Required Properties: 
- interrupts    : Interrupt controller is using

- nr-ports      : Number of SATA ports in use.



Optional Properties:

- phys		: List of phandles to sata phys

- phy-names	: Should be "0", "1", etc, one number per phandle



Example:



	sata@80000 {

		compatible = "marvell,orion-sata";

		reg = <0x80000 0x5000>;

		interrupts = <21>;

		phys = <&sata_phy0>, <&sata_phy1>;

		phy-names = "0", "1";

		nr-ports = <2>;

	}

Documentation/devicetree/bindings/phy/berlin-sata-phy.txt

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@@ -2,7 +2,9 @@ Berlin SATA PHY 
---------------



Required properties:

- compatible: should be "marvell,berlin2q-sata-phy"

- compatible: should be one of

    "marvell,berlin2-sata-phy"

    "marvell,berlin2q-sata-phy"

- address-cells: should be 1

- size-cells: should be 0

- phy-cells: from the generic PHY bindings, must be 1

Documentation/devicetree/bindings/phy/berlin-usb-phy.txt

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* Marvell Berlin USB PHY



Required properties:

- compatible: "marvell,berlin2-usb-phy" or "marvell,berlin2cd-usb-phy"

- reg: base address and length of the registers

- #phys-cells: should be 0

- resets: reference to the reset controller



Example:



	usb-phy@f774000 {

		compatible = "marvell,berlin2-usb-phy";

		reg = <0xf774000 0x128>;

		#phy-cells = <0>;

		resets = <&chip 0x104 14>;

	};

Documentation/devicetree/bindings/phy/phy-miphy28lp.txt

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STMicroelectronics STi MIPHY28LP PHY binding

============================================



This binding describes a miphy device that is used to control PHY hardware

for SATA, PCIe or USB3.



Required properties (controller (parent) node):

- compatible	: Should be "st,miphy28lp-phy".

- st,syscfg	: Should be a phandle of the system configuration register group

		  which contain the SATA, PCIe or USB3 mode setting bits.



Required nodes	:  A sub-node is required for each channel the controller

		   provides. Address range information including the usual

		   'reg' and 'reg-names' properties are used inside these

		   nodes to describe the controller's topology. These nodes

		   are translated by the driver's .xlate() function.



Required properties (port (child) node):

- #phy-cells	: Should be 1 (See second example)

		  Cell after port phandle is device type from:

			- PHY_TYPE_SATA

			- PHY_TYPE_PCI

			- PHY_TYPE_USB3

- reg		: Address and length of the register set for the device.

- reg-names	: The names of the register addresses corresponding to the registers

		  filled in "reg". It can also contain the offset of the system configuration

		  registers used as glue-logic to setup the device for SATA/PCIe or USB3

		  devices.

- resets	: phandle to the parent reset controller.

- reset-names	: Associated name must be "miphy-sw-rst".



Optional properties (port (child) node):

- st,osc-rdy		: to check the MIPHY0_OSC_RDY status in the glue-logic. This

			  is not available in all the MiPHY. For example, for STiH407, only the

			  MiPHY0 has this bit.

- st,osc-force-ext	: to select the external oscillator. This can change from

			  different MiPHY inside the same SoC.

- st,sata_gen		: to select which SATA_SPDMODE has to be set in the SATA system config

			  register.

- st,px_rx_pol_inv	: to invert polarity of RXn/RXp (respectively negative line and positive

			  line).

- st,scc-on		: enable ssc to reduce effects of EMI (only for sata or PCIe).

- st,tx-impedance-comp	: to compensate tx impedance avoiding out of range values.



example:



		miphy28lp_phy: miphy28lp@9b22000 {

			compatible = "st,miphy28lp-phy";

			st,syscfg = <&syscfg_core>;

			#address-cells	= <1>;

			#size-cells	= <1>;

			ranges;



			phy_port0: port@9b22000 {

				reg = <0x9b22000 0xff>,

				      <0x9b09000 0xff>,

				      <0x9b04000 0xff>,

				      <0x114 0x4>, /* sysctrl MiPHY cntrl */

				      <0x818 0x4>, /* sysctrl MiPHY status*/

				      <0xe0  0x4>, /* sysctrl PCIe */

				      <0xec  0x4>; /* sysctrl SATA */

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew",

					    "miphy-ctrl-glue",

					    "miphy-status-glue",

					    "pcie-glue",

					    "sata-glue";

				#phy-cells = <1>;

				st,osc-rdy;

				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY0_SOFTRESET>;

			};



			phy_port1: port@9b2a000 {

				reg = <0x9b2a000 0xff>,

				      <0x9b19000 0xff>,

				      <0x9b14000 0xff>,

				      <0x118 0x4>,

				      <0x81c 0x4>,

				      <0xe4  0x4>,

				      <0xf0  0x4>;

				reg-names = "sata-up",

					    "pcie-up",

					    "pipew",

					    "miphy-ctrl-glue",

					    "miphy-status-glue",

					    "pcie-glue",

					    "sata-glue";

				#phy-cells = <1>;

				st,osc-force-ext;

				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY1_SOFTRESET>;

			};



			phy_port2: port@8f95000 {

				reg = <0x8f95000 0xff>,

				      <0x8f90000 0xff>,

				      <0x11c 0x4>,

				      <0x820 0x4>;

				reg-names = "pipew",

				    "usb3-up",

				    "miphy-ctrl-glue",

				    "miphy-status-glue";

				#phy-cells = <1>;

				reset-names = "miphy-sw-rst";

				resets = <&softreset STIH407_MIPHY2_SOFTRESET>;

			};

		};





Specifying phy control of devices

=================================



Device nodes should specify the configuration required in their "phys"

property, containing a phandle to the miphy device node and an index

specifying which configuration to use, as described in phy-bindings.txt.



example:

		sata0: sata@9b20000  {

			...

			phys		= <&phy_port0 PHY_TYPE_SATA>;

			...

		};



Macro definitions for the supported miphy configuration can be found in:



include/dt-bindings/phy/phy-miphy28lp.h

Documentation/devicetree/bindings/phy/phy-mvebu.txt

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* Marvell MVEBU SATA PHY



Power control for the SATA phy found on Marvell MVEBU SoCs.



This document extends the binding described in phy-bindings.txt



Required properties :



 - reg		   : Offset and length of the register set for the SATA device

 - compatible	   : Should be "marvell,mvebu-sata-phy"

 - clocks	   : phandle of clock and specifier that supplies the device

 - clock-names	   : Should be "sata"



Example:

		sata-phy@84000 {

			compatible = "marvell,mvebu-sata-phy";

			reg = <0x84000 0x0334>;

			clocks = <&gate_clk 15>;

			clock-names = "sata";

			#phy-cells = <0>;

			status = "ok";

		};



Armada 375 USB cluster

----------------------



Armada 375 comes with an USB2 host and device controller and an USB3

controller. The USB cluster control register allows to manage common

features of both USB controllers.



Required properties:



- compatible: "marvell,armada-375-usb-cluster"

- reg: Should contain usb cluster register location and length.

- #phy-cells : from the generic phy bindings, must be 1. Possible

values are 1 (USB2), 2 (USB3).



Example:

		usbcluster: usb-cluster@18400 {

			compatible = "marvell,armada-375-usb-cluster";

			reg = <0x18400 0x4>;

			#phy-cells = <1>

		};