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Commit 840b51dd authored by Shadab Naseem's avatar Shadab Naseem
Browse files

soc: qcom: eud: Add support for EUD TCSR register check 



For some targets like Bengal, eud enablement expects a TCSR register
to be configured first. This would be one time enablement during
drivers probe. Due to this register disabled, eud was not getting
enabled on Bengal platform.
If this register is not configured for EUD, do not enable
eud-tcsr-check-enable parameter.

Change-Id: Iaabfaecf343090d964d06807dcee5ea6a2dca3dc
Signed-off-by: default avatarShadab Naseem <snaseem@codeaurora.org>
parent cfea929f

drivers/soc/qcom/eud.c

+30 −0
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ 
#define UART_ID			0x90

#define MAX_FIFO_SIZE		14



#define EUD_TCSR_ENABLE_BIT	BIT(0)



struct eud_chip {

	struct device			*dev;

	int				eud_irq;
@@ -508,6 +510,8 @@ static int msm_eud_probe(struct platform_device *pdev) 
	struct uart_port *port;

	struct resource *res;

	int ret;

	bool eud_tcsr_check_state;

	phys_addr_t eud_tcsr_check;



	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);

	if (!chip) {
@@ -600,6 +604,32 @@ static int msm_eud_probe(struct platform_device *pdev) 
	port->irq = chip->eud_irq;

	port->ops = &eud_uart_ops;



	/*

	 * Before enabling EUD, check for TCSR register

	 * and if present, enable it.

	 */

	eud_tcsr_check_state = of_property_read_bool(

		pdev->dev.of_node, "qcom,eud-tcsr-check-enable");



	if (eud_tcsr_check_state) {

		res = platform_get_resource_byname(pdev, IORESOURCE_MEM,

					"eud_tcsr_check_reg");

		if (res) {

			eud_tcsr_check = res->start;

			ret = scm_io_write(eud_tcsr_check,

					EUD_TCSR_ENABLE_BIT);

			if (ret) {

				dev_err(&pdev->dev,

				"TCSR scm_io_write failed with rc:%d\n", ret);

				goto error;

			}

		} else {

			dev_err(chip->dev,

				"Failed to get resource for tcsr check!\n");

			goto error;

		}

	}



	ret = uart_add_one_port(&eud_uart_driver, port);

	if (!ret) {

		dev_err(chip->dev, "failed to add uart port!\n");