Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 83fe3be4 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
Browse files

clk: sunxi-ng: sun50i: a64: Add 2x fixed post-divider to MMC module clocks 



On the A64, the MMC module clocks are fixed in the new timing mode,
i.e. they do not have a bit to select the mode. These clocks have
a 2x divider somewhere between the clock and the MMC module.

To be consistent with other SoCs supporting the new timing mode,
we model the 2x divider as a fixed post-divider on the MMC module
clocks.

This patch adds the post-dividers to the MMC clocks.

Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Reviewed-by: default avatarAndre Przywara <andre.przywara@arm.com>
Tested-by: default avatarAndre Przywara <andre.przywara@arm.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 946797aa

drivers/clk/sunxi-ng/ccu-sun50i-a64.c

+37 −20
Original line number Diff line number Diff line
@@ -400,27 +400,44 @@ static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080, 
				  BIT(31),	/* gate */

				  0);



/*

 * MMC clocks are the new timing mode (see A83T & H3) variety, but without

 * the mode switch. This means they have a 2x post divider between the clock

 * and the MMC module. This is not documented in the manual, but is taken

 * into consideration when setting the mmc module clocks in the BSP kernel.

 * Without it, MMC performance is degraded.

 *

 * We model it here to be consistent with other SoCs supporting this mode.

 * The alternative would be to add the 2x multiplier when setting the MMC

 * module clock in the MMC driver, just for the A64.

 */

static const char * const mmc_default_parents[] = { "osc24M", "pll-periph0-2x",

						    "pll-periph1-2x" };

static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mmc_default_parents, 0x088,

static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc0_clk, "mmc0",

					  mmc_default_parents, 0x088,

					  0, 4,		/* M */

					  16, 2,	/* P */

					  24, 2,	/* mux */

					  BIT(31),	/* gate */

					  2,		/* post-div */

					  0);



static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mmc_default_parents, 0x08c,

static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc1_clk, "mmc1",

					  mmc_default_parents, 0x08c,

					  0, 4,		/* M */

					  16, 2,	/* P */

					  24, 2,	/* mux */

					  BIT(31),	/* gate */

					  2,		/* post-div */

					  0);



static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mmc_default_parents, 0x090,

static SUNXI_CCU_MP_WITH_MUX_GATE_POSTDIV(mmc2_clk, "mmc2",

					  mmc_default_parents, 0x090,

					  0, 4,		/* M */

					  16, 2,	/* P */

					  24, 2,	/* mux */

					  BIT(31),	/* gate */

					  2,		/* post-div */

					  0);



static const char * const ts_parents[] = { "osc24M", "pll-periph0", };