Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 83f12503 authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
Browse files

ASoC: davinci-mcasp: Move the FS polarity change out from the switch case 



FS polarity can be either rising or falling edge in McASP. Instead of
accessing the registers in every switch/case set a flag and write the
registers after the switch for the invert configuration.
This change will help when adding support for more formats also.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@linaro.org>
parent 188edc59

sound/soc/davinci/davinci-mcasp.c

+14 −13
Original line number Diff line number Diff line
@@ -272,6 +272,7 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
	struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);

	int ret = 0;

	u32 data_delay;

	bool fs_pol_rising;



	pm_runtime_get_sync(mcasp->dev);

	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
@@ -351,39 +352,39 @@ static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai, 
	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {

	case SND_SOC_DAIFMT_IB_NF:

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);



		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);

		fs_pol_rising = true;

		break;



	case SND_SOC_DAIFMT_NB_IF:

		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);



		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);

		fs_pol_rising = false;

		break;



	case SND_SOC_DAIFMT_IB_IF:

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);



		mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);

		fs_pol_rising = false;

		break;



	case SND_SOC_DAIFMT_NB_NF:

		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);



		mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);

		fs_pol_rising = true;

		break;



	default:

		ret = -EINVAL;

		break;

		goto out;

	}



	if (fs_pol_rising) {

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);

		mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);

	} else {

		mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);

		mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);

	}

out:

	pm_runtime_put_sync(mcasp->dev);