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Commit 83b13249 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "Revert "iommu/arm-smmu: Mark S1 bypass domains as UNMANAGED domains""

parents 3a4ff96a 6cf1c328

arch/arm64/mm/dma-mapping.c

+8 −9
Original line number Diff line number Diff line
@@ -1056,14 +1056,18 @@ iommu_init_mapping(struct device *dev, struct dma_iommu_mapping *mapping) 
static int arm_iommu_get_dma_cookie(struct device *dev,

				    struct dma_iommu_mapping *mapping)

{

	int is_fast = 0;

	int s1_bypass = 0, is_fast = 0;

	int err = 0;



	mutex_lock(&iommu_dma_init_mutex);



	iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS,

					&s1_bypass);

	iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_FAST, &is_fast);



	if (is_fast)

	if (s1_bypass)

		mapping->ops = &arm64_swiotlb_dma_ops;

	else if (is_fast)

		err = fast_smmu_init_mapping(dev, mapping);

	else

		err = iommu_init_mapping(dev, mapping);
@@ -1117,22 +1121,17 @@ static void arm_iommu_setup_dma_ops(struct device *dev, u64 dma_base, u64 size) 
	struct iommu_domain *domain;

	struct iommu_group *group;

	struct dma_iommu_mapping mapping = {0};

	int s1_bypass;



	group = dev->iommu_group;

	if (!group)

		return;



	arm_iommu_get_dma_window(dev, &dma_base, &size);



	domain = iommu_get_domain_for_dev(dev);

	if (!domain)

		return;



	iommu_domain_get_attr(domain, DOMAIN_ATTR_S1_BYPASS, &s1_bypass);

	if (s1_bypass)

		return;



	arm_iommu_get_dma_window(dev, &dma_base, &size);



	/* Allow iommu-debug to call arch_setup_dma_ops to reconfigure itself */

	if (domain->type != IOMMU_DOMAIN_DMA &&

	    !of_device_is_compatible(dev->of_node, "iommu-debug-test")) {

drivers/iommu/arm-smmu.c

+0 −8
Original line number Diff line number Diff line
@@ -439,8 +439,6 @@ static int arm_smmu_setup_default_domain(struct device *dev, 
				struct iommu_domain *domain);

static int __arm_smmu_domain_set_attr(struct iommu_domain *domain,

				    enum iommu_attr attr, void *data);

static int arm_smmu_domain_get_attr(struct iommu_domain *domain,

				    enum iommu_attr attr, void *data);



static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)

{
@@ -2891,7 +2889,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) 
	struct arm_smmu_device *smmu;

	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	int atomic_domain = smmu_domain->attributes & (1 << DOMAIN_ATTR_ATOMIC);

	int s1_bypass = 0;



	if (!fwspec || fwspec->ops != &arm_smmu_ops) {

		dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
@@ -2920,11 +2917,6 @@ static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev) 
	if (ret < 0)

		goto out_power_off;



	ret = arm_smmu_domain_get_attr(domain, DOMAIN_ATTR_S1_BYPASS,

					&s1_bypass);

	if (s1_bypass)

		domain->type = IOMMU_DOMAIN_UNMANAGED;



	/* Do not modify the SIDs, HW is still running */

	if (is_dynamic_domain(domain)) {

		ret = 0;

include/linux/iommu.h

+0 −30
Original line number Diff line number Diff line
@@ -99,8 +99,6 @@ struct iommu_pgtbl_info { 
#define IOMMU_DOMAIN_DMA	(__IOMMU_DOMAIN_PAGING |	\

				 __IOMMU_DOMAIN_DMA_API)



#define to_msm_iommu_ops(_iommu_ops) \

	container_of(_iommu_ops, struct msm_iommu_ops, iommu_ops)



#define IOMMU_DOMAIN_NAME_LEN 32

struct iommu_domain {
@@ -298,34 +296,6 @@ struct iommu_ops { 
	unsigned long pgsize_bitmap;

};



/**

 * struct msm_iommu_ops - standard iommu ops, as well as additional MSM

 * specific iommu ops

 * @map_sg: map a scatter-gather list of physically contiguous memory chunks

 *          to an iommu domain

 * @iova_to_phys_hard: translate iova to physical address using IOMMU hardware

 * @is_iova_coherent: checks coherency of the given iova

 * @trigger_fault: trigger a fault on the device attached to an iommu domain

 * @tlbi_domain: Invalidate all TLBs covering an iommu domain

 * @enable_config_clocks: Enable all config clocks for this domain's IOMMU

 * @disable_config_clocks: Disable all config clocks for this domain's IOMMU

 * @iova_to_pte: translate iova to Page Table Entry (PTE).

 * @iommu_ops: the standard iommu ops

 */

struct msm_iommu_ops {

	size_t (*map_sg)(struct iommu_domain *domain, unsigned long iova,

			 struct scatterlist *sg, unsigned int nents, int prot);

	phys_addr_t (*iova_to_phys_hard)(struct iommu_domain *domain,

					 dma_addr_t iova);

	bool (*is_iova_coherent)(struct iommu_domain *domain, dma_addr_t iova);

	void (*trigger_fault)(struct iommu_domain *domain, unsigned long flags);

	void (*tlbi_domain)(struct iommu_domain *domain);

	int (*enable_config_clocks)(struct iommu_domain *domain);

	void (*disable_config_clocks)(struct iommu_domain *domain);

	uint64_t (*iova_to_pte)(struct iommu_domain *domain, dma_addr_t iova);

	struct iommu_ops iommu_ops;

};



/**

 * struct iommu_device - IOMMU core representation of one IOMMU hardware

 *			 instance