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Commit 83a60ed8 authored by Baptiste Reynal's avatar Baptiste Reynal Committed by Joerg Roedel
Browse files

iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition 



This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys
through ATS1PR".
According to ARM documentation, translation registers are optional even
in SMMUv1, so ID0_S1TS needs to be checked to verify their presence.
Also, we check that the domain is a stage-1 domain.

Signed-off-by: default avatarBaptiste Reynal <b.reynal@virtualopensystems.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent bc465aa9

drivers/iommu/arm-smmu.c

+6 −3
Original line number Diff line number Diff line
@@ -1288,10 +1288,13 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain, 
		return 0;



	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);

	if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS)

	if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&

			smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {

		ret = arm_smmu_iova_to_phys_hard(domain, iova);

	else

	} else {

		ret = ops->iova_to_phys(ops, iova);

	}



	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);



	return ret;
@@ -1556,7 +1559,7 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) 
		return -ENODEV;

	}



	if (smmu->version == 1 || (!(id & ID0_ATOSNS) && (id & ID0_S1TS))) {

	if ((id & ID0_S1TS) && ((smmu->version == 1) || (id & ID0_ATOSNS))) {

		smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;

		dev_notice(smmu->dev, "\taddress translation ops\n");

	}