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Commit 81cd3931 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: camera: Add reset logic for snps phy"

parents 1193ebd5 c7795651

drivers/media/platform/msm/camera_v2/sensor/csiphy/include/msm_csiphy_10_0_0_hwreg.h

+8 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2018, 2020, The Linux Foundation. All rights reserved.

/* Copyright (c) 2018, 2021, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -29,6 +29,9 @@ 
#define mask_enable_clk_B       0x2

#define mask_ctrl_1_A           0x5

#define mask_ctrl_1_B           0xA

#define mask_reset_A            0x1

#define mask_reset_B            0x7

#define mask_shutdown_A         0x3

#define mask_hs_freq_range      0x7F

#define mask_osc_freq_2         0xFF

#define mask_osc_freq_3         0xF00
@@ -57,8 +60,6 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { 
	{0x58C, 0xFF},   /* mipi_csiphy_irq_mask_ctrl_lane_0 */

	{0x5C8, 0xFF},   /* mipi_csiphy_irq_mask_ctrl_lane_clk_0 */

	{0x20, 0x0},     /* mipi_csiphy_rx_sys_7_00 */

	{0x28, 0x43},    /* mipi_csiphy_rx_sys_9_00 */

	{0x380, 0x0},    /* mipi_csiphy_rx_startup_ovr_0_00 */

	{0x384, 0x0},    /* mipi_csiphy_rx_startup_ovr_1_00 */

	{0x388, 0xCC},   /* mipi_csiphy_rx_startup_ovr_2_00 */

	{0x38C, 0x1},    /* mipi_csiphy_rx_startup_ovr_3_00 */
@@ -73,6 +74,10 @@ static struct csiphy_reg_snps_parms_t csiphy_v10_0_0_snps = { 
	{0x12c, 0x0},    /* mipi_csiphy_rx_lane_0_7_00 */

	{0x220, 0x0},    /* mipi_csiphy_rx_lane_1_7_00 */

	{0xCC, 0x0},     /* mipi_csiphy_rx_clk_lane_7_00 */

	{0x1F8, 0x20},   /* mipi_csiphy_rx_lane0_ddl_2_00 */

	{0x1FC, 0x10},   /* mipi_csiphy_rx_lane0_ddl_3_00 */

	{0x22C, 0x80},   /* mipi_csiphy_rx_lane_1_10_00 */

	{0x230, 0x10},   /* mipi_csiphy_rx_lane_1_11_00 */

};



static struct snps_freq_value snps_v100_freq_values[] = {

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.c

+132 −40
Original line number Diff line number Diff line
@@ -259,10 +259,13 @@ static int msm_csiphy_snps_2_lane_config( 
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_sys_7_00.addr + offset);



	msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_sys_9_00.data,

	value = msm_camera_io_r(csiphybase +

		csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_clk_lane_6_00.addr + offset);

	value |= SET_THE_BIT(7);

	msm_camera_io_w(value,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_sys_9_00.addr + offset);

		.mipi_csiphy_rx_clk_lane_6_00.addr + offset);



	msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_startup_ovr_4_00.data,
@@ -292,6 +295,32 @@ static int msm_csiphy_snps_2_lane_config( 
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_rx_cb_2_00.addr + offset);



	if (local_data_rate <= 1500) {

		msm_camera_io_w(

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_2_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_2_00.addr + offset);



		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_3_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane0_ddl_3_00.addr + offset);



		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_10_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_10_00.addr + offset);



		msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_11_00.data,

			csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_lane_1_11_00.addr + offset);

	}

	return 0;

}
@@ -303,7 +332,7 @@ static int msm_csiphy_snps_lane_config( 
	uint16_t lane_mask = 0;

	void __iomem *csiphybase;

	enum snps_csiphy_mode mode = INVALID_MODE;

	uint32_t value, num_tries, num_lanes, offset;

	uint32_t value, num_tries, num_lanes, offset = SNPS_INTERPHY_OFFSET;

	uint32_t clk_mux_reg = 0;



	csiphybase = csiphy_dev->base;
@@ -481,17 +510,6 @@ static int msm_csiphy_snps_lane_config( 
			.mipi_csiphy_rx_clk_lane_7_00.addr +

			SNPS_INTERPHY_OFFSET);



		value = msm_camera_io_r(csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_startup_ovr_0_00.addr +

			SNPS_INTERPHY_OFFSET);

		value |= SET_THE_BIT(0);

		value |= SET_THE_BIT(1);

		msm_camera_io_w(value,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_startup_ovr_0_00.addr +

			SNPS_INTERPHY_OFFSET);



		value = msm_camera_io_r(csiphybase +

			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_startup_ovr_1_00.addr +
@@ -507,6 +525,7 @@ static int msm_csiphy_snps_lane_config( 
			csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_clk_lane_6_00.addr);

		value |= SET_THE_BIT(2);

		value &= ~(SET_THE_BIT(7));

		msm_camera_io_w(value,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

			.mipi_csiphy_rx_clk_lane_6_00.addr);
@@ -516,7 +535,7 @@ static int msm_csiphy_snps_lane_config( 
			.mipi_csiphy_rx_clk_lane_6_00.addr +

			SNPS_INTERPHY_OFFSET);

		value |= SET_THE_BIT(3);

		value |= SET_THE_BIT(7);

		value &= ~(SET_THE_BIT(7));

		value &= ~(SET_THE_BIT(2));

		msm_camera_io_w(value,

			csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg
@@ -578,19 +597,41 @@ static int msm_csiphy_snps_lane_config( 
		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_enable_clk.addr);



	if (mode == TWO_LANE_PHY_A) {

		msm_camera_io_w(mask_reset_A,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



		msm_camera_io_w(mask_ctrl_1_A,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



		value = 0x0;

	if (mode == AGGREGATE_MODE || mode == TWO_LANE_PHY_A)

		value |= mask_ctrl_1_A;

	if (mode == AGGREGATE_MODE || mode == TWO_LANE_PHY_B)

		value |= mask_ctrl_1_B;

	msm_camera_io_w(value,

		num_tries = 0;



		do {

			num_tries++;

			value = msm_camera_io_r(csiphybase +

				csiphy_dev->ctrl_reg->csiphy_snps_reg

				.mipi_csiphy_rx_startup_obs_2_00.addr);

			if ((value | SET_THE_BIT(4)) == value)

				break;

			usleep_range(100, 150);

		} while (num_tries < 6);

		if ((value | SET_THE_BIT(4)) != value) {

			pr_err("%s: SNPS phy config failed\n", __func__);

			return -EINVAL;

		}

	}



	if (mode == TWO_LANE_PHY_B) {

		msm_camera_io_w(mask_reset_B,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



	if (mode == AGGREGATE_MODE || mode == TWO_LANE_PHY_A)

		offset = 0x0;

	else

		offset = SNPS_INTERPHY_OFFSET;

		msm_camera_io_w(mask_ctrl_1_A|mask_ctrl_1_B,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



		value = 0x0;

		num_tries = 0;
@@ -609,6 +650,57 @@ static int msm_csiphy_snps_lane_config( 
			pr_err("%s: SNPS phy config failed\n", __func__);

			return -EINVAL;

		}

	}



	if (mode == AGGREGATE_MODE) {

		msm_camera_io_w(mask_shutdown_A,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



		msm_camera_io_w(mask_reset_B,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



		value = 0x0;

		num_tries = 0;



		do {

			num_tries++;

			value = msm_camera_io_r(csiphybase +

				csiphy_dev->ctrl_reg->csiphy_snps_reg

				.mipi_csiphy_rx_startup_obs_2_00.addr);

			if ((value | SET_THE_BIT(4)) == value)

				break;

			usleep_range(100, 150);

		} while (num_tries < 6);



		if ((value | SET_THE_BIT(4)) != value) {

			pr_err("%s: SNPS phy config failed\n", __func__);

			return -EINVAL;

		}



		msm_camera_io_w(mask_ctrl_1_A|mask_ctrl_1_B,

		csiphybase + csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_ctrl_1.addr);



		value = 0x0;

		num_tries = 0;



		do {

			num_tries++;

			value = msm_camera_io_r(csiphybase +

				csiphy_dev->ctrl_reg->csiphy_snps_reg

				.mipi_csiphy_rx_startup_obs_2_00.addr + offset);

			if ((value | SET_THE_BIT(4)) == value)

				break;

			usleep_range(100, 150);

		} while (num_tries < 6);



		if ((value | SET_THE_BIT(4)) != value) {

			pr_err("%s: SNPS phy config failed\n", __func__);

			return -EINVAL;

		}

	}



	msm_camera_io_w(csiphy_dev->ctrl_reg->csiphy_snps_reg

		.mipi_csiphy_force_mode.data,

drivers/media/platform/msm/camera_v2/sensor/csiphy/msm_csiphy.h

+5 −3
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/* Copyright (c) 2011-2018, 2020, The Linux Foundation. All rights reserved.

/* Copyright (c) 2011-2018, 2020-2021, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -84,8 +84,6 @@ struct csiphy_reg_snps_parms_t { 
	struct csiphy_reg_t mipi_csiphy_irq_mask_ctrl_lane_0;

	struct csiphy_reg_t mipi_csiphy_irq_mask_ctrl_lane_clk_0;

	struct csiphy_reg_t mipi_csiphy_rx_sys_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_sys_9_00;

	struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_0_00;

	struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_1_00;

	struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_2_00;

	struct csiphy_reg_t mipi_csiphy_rx_startup_ovr_3_00;
@@ -100,6 +98,10 @@ struct csiphy_reg_snps_parms_t { 
	struct csiphy_reg_t mipi_csiphy_rx_lane_0_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_clk_lane_7_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_2_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane0_ddl_3_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_10_00;

	struct csiphy_reg_t mipi_csiphy_rx_lane_1_11_00;

};



struct csiphy_reg_3ph_parms_t {