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Commit 81c7e03a authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Tero Kristo
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CLK: TI: clk-54xx: Set the rate for dpll_abe_m2x2_ck 



In order to get correct clock dividers for AESS/ABE we need to set the
dpll_abe_m2x2_ck rate to be double of dpll_abe_ck.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent 9ac33b0c

drivers/clk/ti/clk-54xx.c

+6 −0
Original line number Diff line number Diff line
@@ -240,6 +240,12 @@ int __init omap5xxx_dt_clk_init(void) 
	if (rc)

		pr_err("%s: failed to configure ABE DPLL!\n", __func__);



	abe_dpll = clk_get_sys(NULL, "dpll_abe_m2x2_ck");

	if (!rc)

		rc = clk_set_rate(abe_dpll, OMAP5_DPLL_ABE_DEFFREQ * 2);

	if (rc)

		pr_err("%s: failed to configure ABE m2x2 DPLL!\n", __func__);



	usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");

	rc = clk_set_rate(usb_dpll, OMAP5_DPLL_USB_DEFFREQ);

	if (rc)