Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 816d2206 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2015-11-06' of... 

Merge tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel into drm-next

Here's a handful of i915 fixes for drm-next/v4.4. Imre's commit alone
should address the remaining warnings galore you experienced on
Skylake. Almost all of the rest are also fixes against user or QA
reported bugs, with references.

* tag 'drm-intel-next-fixes-2015-11-06' of git://anongit.freedesktop.org/drm-intel:
  drm/i915/skl: disable display side power well support for now
  drm/i915: Extend DSL readout fix to BDW and SKL.
  drm/i915: Do graphics device reset under forcewake
  drm/i915: Skip fence installation for objects with rotated views (v4)
  drm/i915: add quirk to enable backlight on Dell Chromebook 11 (2015)
  drm/i915/skl: Prevent unclaimed register writes on skylake.
  drm/i915: disable CPU PWM also on LPT/SPT backlight disable
  drm/i915: Fix maxfifo watermark calc on vlv cursor planes
  drm/i915: add hotplug activation period to hotplug update mask
parents d0baf921 1b0e3a04

drivers/gpu/drm/i915/i915_irq.c

+5 −4
Original line number Diff line number Diff line
@@ -749,7 +749,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 
	 * problem.  We may need to extend this to include other platforms,

	 * but so far testing only shows the problem on HSW.

	 */

	if (IS_HASWELL(dev) && !position) {

	if (HAS_DDI(dev) && !position) {

		int i, temp;



		for (i = 0; i < 100; i++) {
@@ -4236,8 +4236,9 @@ static void i915_hpd_irq_setup(struct drm_device *dev) 


	/* Ignore TV since it's buggy */

	i915_hotplug_interrupt_update_locked(dev_priv,

				      (HOTPLUG_INT_EN_MASK

				       | CRT_HOTPLUG_VOLTAGE_COMPARE_MASK),

					     HOTPLUG_INT_EN_MASK |

					     CRT_HOTPLUG_VOLTAGE_COMPARE_MASK |

					     CRT_HOTPLUG_ACTIVATION_PERIOD_64,

					     hotplug_en);

}

drivers/gpu/drm/i915/i915_params.c

+3 −2
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ struct i915_params i915 __read_mostly = { 
	.enable_ppgtt = -1,

	.enable_psr = 0,

	.preliminary_hw_support = IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT),

	.disable_power_well = 1,

	.disable_power_well = -1,

	.enable_ips = 1,

	.prefault_disable = 0,

	.load_detect_test = 0,
@@ -127,7 +127,8 @@ MODULE_PARM_DESC(preliminary_hw_support, 


module_param_named_unsafe(disable_power_well, i915.disable_power_well, int, 0600);

MODULE_PARM_DESC(disable_power_well,

	"Disable the power well when possible (default: true)");

	"Disable display power wells when possible "

	"(-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)");



module_param_named_unsafe(enable_ips, i915.enable_ips, int, 0600);

MODULE_PARM_DESC(enable_ips, "Enable IPS (default: true)");

drivers/gpu/drm/i915/intel_display.c

+23 −16
Original line number Diff line number Diff line
@@ -2389,6 +2389,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, 
	 * framebuffer compression.  For simplicity, we always install

	 * a fence as the cost is not that onerous.

	 */

	if (view.type == I915_GGTT_VIEW_NORMAL) {

		ret = i915_gem_object_get_fence(obj);

		if (ret == -EDEADLK) {

			/*
@@ -2405,6 +2406,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane, 
			goto err_unpin;



		i915_gem_object_pin_fence(obj);

	}



	dev_priv->mm.interruptible = true;

	intel_runtime_pm_put(dev_priv);
@@ -2430,7 +2432,9 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, 
	ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);

	WARN_ONCE(ret, "Couldn't get view from plane state!");



	if (view.type == I915_GGTT_VIEW_NORMAL)

		i915_gem_object_unpin_fence(obj);



	i915_gem_object_unpin_from_display_plane(obj, &view);

}
@@ -14695,6 +14699,9 @@ static struct intel_quirk intel_quirks[] = { 


	/* Dell Chromebook 11 */

	{ 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },



	/* Dell Chromebook 11 (2015 version) */

	{ 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },

};



static void intel_init_quirks(struct drm_device *dev)

drivers/gpu/drm/i915/intel_panel.c

+14 −0
Original line number Diff line number Diff line
@@ -732,6 +732,20 @@ static void lpt_disable_backlight(struct intel_connector *connector) 


	intel_panel_actually_set_backlight(connector, 0);



	/*

	 * Although we don't support or enable CPU PWM with LPT/SPT based

	 * systems, it may have been enabled prior to loading the

	 * driver. Disable to avoid warnings on LCPLL disable.

	 *

	 * This needs rework if we need to add support for CPU PWM on PCH split

	 * platforms.

	 */

	tmp = I915_READ(BLC_PWM_CPU_CTL2);

	if (tmp & BLM_PWM_ENABLE) {

		DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n");

		I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);

	}



	tmp = I915_READ(BLC_PWM_PCH_CTL1);

	I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);

}

drivers/gpu/drm/i915/intel_pm.c

+6 −1
Original line number Diff line number Diff line
@@ -1135,7 +1135,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc) 
		case DRM_PLANE_TYPE_CURSOR:

			for (level = 0; level < wm_state->num_levels; level++)

				wm_state->sr[level].cursor =

					wm_state->sr[level].cursor;

					wm_state->wm[level].cursor;

			break;

		case DRM_PLANE_TYPE_PRIMARY:

			for (level = 0; level < wm_state->num_levels; level++)
@@ -2818,7 +2818,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, 
	int plane;

	u32 val;



	memset(ddb, 0, sizeof(*ddb));



	for_each_pipe(dev_priv, pipe) {

		if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))

			continue;



		for_each_plane(dev_priv, pipe, plane) {

			val = I915_READ(PLANE_BUF_CFG(pipe, plane));

			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],