Merge "ARM: dts: msm: Add QUPV3 SE dt node for UART on lito" (80a70db0) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm64/boot/dts/qcom/lito-pinctrl.dtsi

+97 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,103 @@
		interrupt-controller;
		#interrupt-cells = <2>;

		qupv3_se2_2uart_pins: qupv3_se2_2uart_pins {
		qupv3_se2_2uart_active: qupv3_se2_2uart_active {
		mux {
		pins = "gpio36", "gpio37";
		function = "qup02";
		};

		config {
		pins = "gpio36", "gpio37";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se2_2uart_sleep: qupv3_se2_2uart_sleep {
		mux {
		pins = "gpio36", "gpio37";
		function = "gpio";
		};

		config {
		pins = "gpio36", "gpio37";
		drive-strength = <2>;
		bias-pull-down;
		};
		};
		};

		qupv3_se5_4uart_pins: qupv3_se5_4uart_pins {
		qupv3_se5_ctsrx: qupv3_se5_ctsrx {
		mux {
		pins = "gpio38", "gpio41";
		function = "qup05";
		};

		config {
		pins = "gpio38", "gpio41";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se5_rts: qupv3_se5_rts {
		mux {
		pins = "gpio39";
		function = "qup05";
		};

		config {
		pins = "gpio39";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se5_tx: qupv3_se5_tx {
		mux {
		pins = "gpio40";
		function = "qup05";
		};

		config {
		pins = "gpio40";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se8_2uart_pins: qupv3_se8_2uart_pins {
		qupv3_se8_2uart_active: qupv3_se8_2uart_active {
		mux {
		pins = "gpio51", "gpio52";
		function = "qup12";
		};

		config {
		pins = "gpio51", "gpio52";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep {
		mux {
		pins = "gpio51", "gpio52";
		function = "gpio";
		};

		config {
		pins = "gpio51", "gpio52";
		drive-strength = <2>;
		bias-pull-down;
		};
		};
		};

		ufs_dev_reset_assert: ufs_dev_reset_assert {
		config {
		pins = "ufs_reset";

arch/arm64/boot/dts/qcom/lito-qupv3.dtsi

0 → 100644

+85 −0

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
		*/

		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/QUPv3_0 /
		qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_0>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		iommus = <&apps_smmu 0x4e3 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
		qcom,iommu-dma = "bypass";
		};

		/* Debug UART Instance for RUMI platform */
		qupv3_se2_2uart: qcom,qup_uart@888000 {
		compatible = "qcom,msm-geni-console";
		reg = <0x888000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_2uart_active>;
		pinctrl-1 = <&qupv3_se2_2uart_sleep>;
		interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		/* 4-wire UART */
		qupv3_se5_4uart: qcom,qup_uart@894000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0x894000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
		<&qupv3_se5_tx>;
		pinctrl-1 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
		<&qupv3_se5_tx>;
		interrupts-extended = <&intc GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>,
		<&tlmm 41 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_0>;
		qcom,wakeup-byte = <0xFD>;
		status = "disabled";
		};

		/QUPv3_1 /
		qupv3_1: qcom,qupv3_1_geni_se@9c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x9c0000 0x2000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_QUP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH1>;
		iommus = <&apps_smmu 0x023 0x0>;
		qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
		qcom,iommu-dma = "bypass";
		};

		/* 2-wire UART */
		qupv3_se8_2uart: qcom,qup_uart@988000 {
		compatible = "qcom,msm-geni-console";
		reg = <0x988000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se8_2uart_active>;
		pinctrl-1 = <&qupv3_se8_2uart_sleep>;
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};
		};

arch/arm64/boot/dts/qcom/lito-rumi.dtsi

+9 −0

Original line number	Diff line number	Diff line
		@@ -44,6 +44,15 @@
		};
		};

		&qupv3_se8_2uart {
		status = "disabled";
		};

		/RUMI UART console/
		&qupv3_se2_2uart {
		status = "ok";
		};

		&wdog {
		status = "disabled";
		};

arch/arm64/boot/dts/qcom/lito.dtsi

+3 −0

Original line number	Diff line number	Diff line
		@@ -24,6 +24,7 @@
		interrupt-parent = <&intc>;

		aliases {
		serial0 = &qupv3_se2_2uart; /RUMI/
		ufshc1 = &ufshc_mem; /* Embedded UFS slot */
		};

		@@ -1390,3 +1391,5 @@
		&mvs1_gdsc {
		status = "ok";
		};

		#include "lito-qupv3.dtsi"