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Commit 8043f93d authored by Mao Jinlong's avatar Mao Jinlong Committed by Gerrit - the friendly Code Review server
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byte-cntr: Don't set csr registers when read_active is false 



When read_active is false, tmc-etr may be disabled. If try to access
csr registers, there will be access issue as qdss clock is disabled.
So don't set csr registers when read_active is false.

Change-Id: I2bfac6b642669a77f45e9f628c2bc68524f9d571
Signed-off-by: default avatarMao Jinlong <jinlmao@codeaurora.org>
parent 8fbc286d

drivers/hwtracing/coresight/coresight-byte-cntr.c

+6 −1
Original line number Original line Diff line number Diff line
@@ -217,7 +217,12 @@ void usb_bypass_stop(struct byte_cntr *byte_cntr_data) 
		return;

		return;





	mutex_lock(&byte_cntr_data->usb_bypass_lock);

	mutex_lock(&byte_cntr_data->usb_bypass_lock);

	if (byte_cntr_data->read_active)

		byte_cntr_data->read_active = false;

		byte_cntr_data->read_active = false;

	else {

		mutex_unlock(&byte_cntr_data->usb_bypass_lock);

		return;

	}

	wake_up(&byte_cntr_data->usb_wait_wq);

	wake_up(&byte_cntr_data->usb_wait_wq);

	pr_info("coresight: stop usb bypass\n");

	pr_info("coresight: stop usb bypass\n");

	coresight_csr_set_byte_cntr(byte_cntr_data->csr, 0);

	coresight_csr_set_byte_cntr(byte_cntr_data->csr, 0);