thermal: samsung: Remove support for Exynos5440

	       "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4

			Exynos5420 (Must pass triminfo base and triminfo clock)

               "samsung,exynos5433-tmu"

	       "samsung,exynos5440-tmu"

	       "samsung,exynos7-tmu"

- interrupt-parent : The phandle for the interrupt controller

- reg : Address range of the thermal registers. For soc's which has multiple

		#thermal-sensor-cells = <0>;

	};

Example 2):

	tmuctrl_0: tmuctrl@160118 {

		compatible = "samsung,exynos5440-tmu";

		reg = <0x160118 0x230>, <0x160368 0x10>;

		interrupts = <0 58 0>;

		clocks = <&clock 21>;

		clock-names = "tmu_apbif";

		#thermal-sensor-cells = <0>;

	};

Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")

Example 2): (In case of Exynos5420 "with misplaced TRIMINFO register")

	tmu_cpu2: tmu@10068000 {

		compatible = "samsung,exynos5420-tmu-ext-triminfo";

		reg = <0x10068000 0x100>, <0x1006c000 0x4>;

#define EXYNOS5433_G3D_BASE			0x10070000

/*exynos5440 specific registers*/

#define EXYNOS5440_TMU_S0_7_TRIM		0x000

#define EXYNOS5440_TMU_S0_7_CTRL		0x020

#define EXYNOS5440_TMU_S0_7_DEBUG		0x040

#define EXYNOS5440_TMU_S0_7_TEMP		0x0f0

#define EXYNOS5440_TMU_S0_7_TH0			0x110

#define EXYNOS5440_TMU_S0_7_TH1			0x130

#define EXYNOS5440_TMU_S0_7_TH2			0x150

#define EXYNOS5440_TMU_S0_7_IRQEN		0x210

#define EXYNOS5440_TMU_S0_7_IRQ			0x230

/* exynos5440 common registers */

#define EXYNOS5440_TMU_IRQ_STATUS		0x000

#define EXYNOS5440_TMU_PMIN			0x004

#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0

#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1

#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2

#define EXYNOS5440_TMU_INTEN_RISE3_SHIFT	3

#define EXYNOS5440_TMU_INTEN_FALL0_SHIFT	4

#define EXYNOS5440_TMU_TH_RISE4_SHIFT		24

#define EXYNOS5440_EFUSE_SWAP_OFFSET		8

/* Exynos7 specific registers */

#define EXYNOS7_THD_TEMP_RISE7_6		0x50

#define EXYNOS7_THD_TEMP_FALL7_6		0x60

	SOC_ARCH_EXYNOS5420,

	SOC_ARCH_EXYNOS5420_TRIMINFO,

	SOC_ARCH_EXYNOS5433,

	SOC_ARCH_EXYNOS5440,

	SOC_ARCH_EXYNOS7,

};

	return ret;

}

static int exynos5440_tmu_initialize(struct platform_device *pdev)

{

	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	unsigned int trim_info = 0, con, rising_threshold;

	int threshold_code;

	int crit_temp = 0;

	/*

	 * For exynos5440 soc triminfo value is swapped between TMU0 and

	 * TMU2, so the below logic is needed.

	 */

	switch (data->id) {

	case 0:

		trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET +

				 EXYNOS5440_TMU_S0_7_TRIM);

		break;

	case 1:

		trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM);

		break;

	case 2:

		trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET +

				  EXYNOS5440_TMU_S0_7_TRIM);

	}

	sanitize_temp_error(data, trim_info);

	/* Write temperature code for rising and falling threshold */

	rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0);

	rising_threshold = get_th_reg(data, rising_threshold, false);

	writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0);

	writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1);

	data->tmu_clear_irqs(data);

	/* if last threshold limit is also present */

	if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) {

		threshold_code = temp_to_code(data, crit_temp / MCELSIUS);

		/* 5th level to be assigned in th2 reg */

		rising_threshold =

			threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT;

		writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2);

		con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL);

		con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT);

		writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);

	}

	/* Clear the PMIN in the common TMU register */

	if (!data->id)

		writel(0, data->base_second + EXYNOS5440_TMU_PMIN);

	return 0;

}

static int exynos7_tmu_initialize(struct platform_device *pdev)

{

	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	writel(con, data->base + EXYNOS_TMU_REG_CONTROL);

}

static void exynos5440_tmu_control(struct platform_device *pdev, bool on)

{

	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	struct thermal_zone_device *tz = data->tzd;

	unsigned int con, interrupt_en;

	con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL));

	if (on) {

		con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT);

		interrupt_en =

			(of_thermal_is_trip_valid(tz, 3)

			 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) |

			(of_thermal_is_trip_valid(tz, 2)

			 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) |

			(of_thermal_is_trip_valid(tz, 1)

			 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) |

			(of_thermal_is_trip_valid(tz, 0)

			 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT);

		interrupt_en |=

			interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT;

	} else {

		con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT);

		interrupt_en = 0; /* Disable all interrupts */

	}

	writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN);

	writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL);

}

static void exynos7_tmu_control(struct platform_device *pdev, bool on)

{

	struct exynos_tmu_data *data = platform_get_drvdata(pdev);

	if (temp) {

		temp /= MCELSIUS;

		if (data->soc != SOC_ARCH_EXYNOS5440) {

		val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT);

		val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT);

		}

		if (data->soc == SOC_ARCH_EXYNOS7) {

			val &= ~(EXYNOS7_EMUL_DATA_MASK <<

				EXYNOS7_EMUL_DATA_SHIFT);

	writel(val, data->base + emul_con);

}

static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data,

					 int temp)

{

	unsigned int val;

	val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG);

	val = get_emul_con_reg(data, val, temp);

	writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG);

}

static int exynos_tmu_set_emulation(void *drv_data, int temp)

{

	struct exynos_tmu_data *data = drv_data;

}

#else

#define exynos4412_tmu_set_emulation NULL

#define exynos5440_tmu_set_emulation NULL

static int exynos_tmu_set_emulation(void *drv_data, int temp)

	{ return -EINVAL; }

#endif /* CONFIG_THERMAL_EMULATION */

	return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP);

}

static int exynos5440_tmu_read(struct exynos_tmu_data *data)

{

	return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP);

}

static int exynos7_tmu_read(struct exynos_tmu_data *data)

{

	return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) &

{

	struct exynos_tmu_data *data = container_of(work,

			struct exynos_tmu_data, irq_work);

	unsigned int val_type;

	if (!IS_ERR(data->clk_sec))

		clk_enable(data->clk_sec);

	/* Find which sensor generated this interrupt */

	if (data->soc == SOC_ARCH_EXYNOS5440) {

		val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS);

		if (!((val_type >> data->id) & 0x1))

			goto out;

	}

	if (!IS_ERR(data->clk_sec))

		clk_disable(data->clk_sec);

	clk_disable(data->clk);

	mutex_unlock(&data->lock);

out:

	enable_irq(data->irq);

}

	writel(val_irq, data->base + tmu_intclear);

}

static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data)

{

	unsigned int val_irq;

	val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ);

	/* clear the interrupts */

	writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ);

}

static irqreturn_t exynos_tmu_irq(int irq, void *id)

{

	struct exynos_tmu_data *data = id;

	}, {

		.compatible = "samsung,exynos5433-tmu",

		.data = (const void *)SOC_ARCH_EXYNOS5433,

	}, {

		.compatible = "samsung,exynos5440-tmu",

		.data = (const void *)SOC_ARCH_EXYNOS5440,

	}, {

		.compatible = "samsung,exynos7-tmu",

		.data = (const void *)SOC_ARCH_EXYNOS7,

		data->min_efuse_value = 40;

		data->max_efuse_value = 150;

		break;

	case SOC_ARCH_EXYNOS5440:

		data->tmu_initialize = exynos5440_tmu_initialize;

		data->tmu_control = exynos5440_tmu_control;

		data->tmu_read = exynos5440_tmu_read;

		data->tmu_set_emulation = exynos5440_tmu_set_emulation;

		data->tmu_clear_irqs = exynos5440_tmu_clear_irqs;

		data->ntrip = 4;

		data->gain = 5;

		data->reference_voltage = 16;

		data->efuse_value = 0x5d2d;

		data->min_efuse_value = 16;

		data->max_efuse_value = 76;

		break;

	case SOC_ARCH_EXYNOS7:

		data->tmu_initialize = exynos7_tmu_initialize;

		data->tmu_control = exynos7_tmu_control;

	 * Check if the TMU shares some registers and then try to map the

	 * memory of common registers.

	 */

	if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO &&

	    data->soc != SOC_ARCH_EXYNOS5440)

	if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO)

		return 0;

	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {