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Commit 7fe2ac68 authored by James Bottomley's avatar James Bottomley
Browse files

Merge branch 'flushing' into for-linus

parents 2e7bad5f b7d45818

arch/parisc/include/asm/cacheflush.h

+4 −1
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 


#include <linux/mm.h>

#include <linux/uaccess.h>

#include <asm/tlbflush.h>



/* The usual comment is "Caches aren't brain-dead on the <architecture>".

 * Unfortunately, that doesn't apply to PA-RISC. */
@@ -112,9 +113,11 @@ void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr); 
static inline void

flush_anon_page(struct vm_area_struct *vma, struct page *page, unsigned long vmaddr)

{

	if (PageAnon(page))

	if (PageAnon(page)) {

		flush_tlb_page(vma, vmaddr);

		flush_dcache_page_asm(page_to_phys(page), vmaddr);

	}

}



#ifdef CONFIG_DEBUG_RODATA

void mark_rodata_ro(void);

arch/parisc/include/asm/pgtable.h

+7 −2
Original line number Diff line number Diff line
@@ -177,7 +177,10 @@ struct vm_area_struct; 


#define _PAGE_TABLE	(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_ACCESSED)

#define _PAGE_CHG_MASK	(PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)

#define _PAGE_KERNEL	(_PAGE_PRESENT | _PAGE_EXEC | _PAGE_READ | _PAGE_WRITE | _PAGE_DIRTY | _PAGE_ACCESSED)

#define _PAGE_KERNEL_RO	(_PAGE_PRESENT | _PAGE_READ | _PAGE_DIRTY | _PAGE_ACCESSED)

#define _PAGE_KERNEL_EXEC	(_PAGE_KERNEL_RO | _PAGE_EXEC)

#define _PAGE_KERNEL_RWX	(_PAGE_KERNEL_EXEC | _PAGE_WRITE)

#define _PAGE_KERNEL		(_PAGE_KERNEL_RO | _PAGE_WRITE)



/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds

 * are page-aligned, we don't care about the PAGE_OFFSET bits, except
@@ -208,7 +211,9 @@ struct vm_area_struct; 
#define PAGE_COPY       PAGE_EXECREAD

#define PAGE_RWX        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_READ | _PAGE_WRITE | _PAGE_EXEC |_PAGE_ACCESSED)

#define PAGE_KERNEL	__pgprot(_PAGE_KERNEL)

#define PAGE_KERNEL_RO	__pgprot(_PAGE_KERNEL & ~_PAGE_WRITE)

#define PAGE_KERNEL_EXEC	__pgprot(_PAGE_KERNEL_EXEC)

#define PAGE_KERNEL_RWX	__pgprot(_PAGE_KERNEL_RWX)

#define PAGE_KERNEL_RO	__pgprot(_PAGE_KERNEL_RO)

#define PAGE_KERNEL_UNC	__pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)

#define PAGE_GATEWAY    __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED | _PAGE_GATEWAY| _PAGE_READ)

arch/parisc/kernel/cache.c

+12 −1
Original line number Diff line number Diff line
@@ -304,10 +304,20 @@ void flush_dcache_page(struct page *page) 
		offset = (pgoff - mpnt->vm_pgoff) << PAGE_SHIFT;

		addr = mpnt->vm_start + offset;



		/* The TLB is the engine of coherence on parisc: The

		 * CPU is entitled to speculate any page with a TLB

		 * mapping, so here we kill the mapping then flush the

		 * page along a special flush only alias mapping.

		 * This guarantees that the page is no-longer in the

		 * cache for any process and nor may it be

		 * speculatively read in (until the user or kernel

		 * specifically accesses it, of course) */



		flush_tlb_page(mpnt, addr);

		if (old_addr == 0 || (old_addr & (SHMLBA - 1)) != (addr & (SHMLBA - 1))) {

			__flush_cache_page(mpnt, addr, page_to_phys(page));

			if (old_addr)

				printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? mpnt->vm_file->f_path.dentry->d_name.name : "(null)");

				printk(KERN_ERR "INEQUIVALENT ALIASES 0x%lx and 0x%lx in file %s\n", old_addr, addr, mpnt->vm_file ? (char *)mpnt->vm_file->f_path.dentry->d_name.name : "(null)");

			old_addr = addr;

		}

	}
@@ -499,6 +509,7 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long 
{

	BUG_ON(!vma->vm_mm->context);



	flush_tlb_page(vma, vmaddr);

	__flush_cache_page(vma, vmaddr, page_to_phys(pfn_to_page(pfn)));



}

arch/parisc/kernel/entry.S

+3 −0
Original line number Diff line number Diff line
@@ -692,6 +692,9 @@ ENTRY(fault_vector_11) 
END(fault_vector_11)



#endif

	/* Fault vector is separately protected and *must* be on its own page */

	.align		PAGE_SIZE

ENTRY(end_fault_vector)



	.import		handle_interruption,code

	.import		do_cpu_irq_mask,code

arch/parisc/kernel/head.S

+3 −2
Original line number Diff line number Diff line
@@ -106,8 +106,9 @@ $bss_loop: 
#endif





	/* Now initialize the PTEs themselves */

	ldo		0+_PAGE_KERNEL(%r0),%r3 /* Hardwired 0 phys addr start */

	/* Now initialize the PTEs themselves.  We use RWX for

	 * everything ... it will get remapped correctly later */

	ldo		0+_PAGE_KERNEL_RWX(%r0),%r3 /* Hardwired 0 phys addr start */

	ldi		(1<<(KERNEL_INITIAL_ORDER-PAGE_SHIFT)),%r11 /* PFN count */

	load32		PA(pg0),%r1