Merge branch 'for_3.2/pm-cleanup-2' of git://github.com/khilman/linux-omap-pm into fixes (7fd92b56) · Commits · e / devices / android_kernel_oneplus_sm7250

arch/arm/mach-omap2/id.c

+4 −1

Original line number	Original line	Diff line number	Diff line
	@@ -187,8 +187,11 @@ static void __init omap3_check_features(void)
	OMAP3_CHECK_FEATURE(status, ISP);		OMAP3_CHECK_FEATURE(status, ISP);
	if (cpu_is_omap3630())		if (cpu_is_omap3630())
	omap_features \|= OMAP3_HAS_192MHZ_CLK;		omap_features \|= OMAP3_HAS_192MHZ_CLK;
	if (!cpu_is_omap3505() && !cpu_is_omap3517())		if (cpu_is_omap3430() \|\| cpu_is_omap3630())
	omap_features \|= OMAP3_HAS_IO_WAKEUP;		omap_features \|= OMAP3_HAS_IO_WAKEUP;
			if (cpu_is_omap3630() \|\| omap_rev() == OMAP3430_REV_ES3_1 \|\|
			omap_rev() == OMAP3430_REV_ES3_1_2)
			omap_features \|= OMAP3_HAS_IO_CHAIN_CTRL;

	omap_features \|= OMAP3_HAS_SDRC;		omap_features \|= OMAP3_HAS_SDRC;

arch/arm/mach-omap2/pm34xx.c

+37 −33

Original line number	Original line	Diff line number	Diff line
	@@ -99,7 +99,6 @@ static void omap3_enable_io_chain(void)
	{		{
	int timeout = 0;		int timeout = 0;

	if (omap_rev() >= OMAP3430_REV_ES3_1) {
	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
	PM_WKEN);		PM_WKEN);
	/* Do a readback to assure write has been done */		/* Do a readback to assure write has been done */
	@@ -109,19 +108,16 @@ static void omap3_enable_io_chain(void)
	OMAP3430_ST_IO_CHAIN_MASK)) {		OMAP3430_ST_IO_CHAIN_MASK)) {
	timeout++;		timeout++;
	if (timeout > 1000) {		if (timeout > 1000) {
	printk(KERN_ERR "Wake up daisy chain "		pr_err("Wake up daisy chain activation failed.\n");
	"activation failed.\n");
	return;		return;
	}		}
	omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,		omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
	WKUP_MOD, PM_WKEN);		WKUP_MOD, PM_WKEN);
	}		}
	}		}
	}

	static void omap3_disable_io_chain(void)		static void omap3_disable_io_chain(void)
	{		{
	if (omap_rev() >= OMAP3430_REV_ES3_1)
	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
	PM_WKEN);		PM_WKEN);
	}		}
	@@ -363,7 +359,6 @@ void omap_sram_idle(void)
	printk(KERN_ERR "Invalid mpu state in sram_idle\n");		printk(KERN_ERR "Invalid mpu state in sram_idle\n");
	return;		return;
	}		}
	pwrdm_pre_transition();

	/* NEON control */		/* NEON control */
	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)		if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
	@@ -376,6 +371,7 @@ void omap_sram_idle(void)
	(per_next_state < PWRDM_POWER_ON \|\|		(per_next_state < PWRDM_POWER_ON \|\|
	core_next_state < PWRDM_POWER_ON)) {		core_next_state < PWRDM_POWER_ON)) {
	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
			if (omap3_has_io_chain_ctrl())
	omap3_enable_io_chain();		omap3_enable_io_chain();
	}		}

	@@ -386,6 +382,8 @@ void omap_sram_idle(void)
	if (!console_trylock())		if (!console_trylock())
	goto console_still_active;		goto console_still_active;

			pwrdm_pre_transition();

	/* PER */		/* PER */
	if (per_next_state < PWRDM_POWER_ON) {		if (per_next_state < PWRDM_POWER_ON) {
	per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
	@@ -414,8 +412,9 @@ void omap_sram_idle(void)
	* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.		* of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
	* Hence store/restore the SDRC_POWER register here.		* Hence store/restore the SDRC_POWER register here.
	*/		*/
	if (omap_rev() >= OMAP3430_REV_ES3_0 &&		if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	omap_type() != OMAP2_DEVICE_TYPE_GP &&		(omap_type() == OMAP2_DEVICE_TYPE_EMU \|\|
			omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
	core_next_state == PWRDM_POWER_OFF)		core_next_state == PWRDM_POWER_OFF)
	sdrc_pwr = sdrc_read_reg(SDRC_POWER);		sdrc_pwr = sdrc_read_reg(SDRC_POWER);

	@@ -432,8 +431,9 @@ void omap_sram_idle(void)
	omap34xx_do_sram_idle(save_state);		omap34xx_do_sram_idle(save_state);

	/* Restore normal SDRC POWER settings */		/* Restore normal SDRC POWER settings */
	if (omap_rev() >= OMAP3430_REV_ES3_0 &&		if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	omap_type() != OMAP2_DEVICE_TYPE_GP &&		(omap_type() == OMAP2_DEVICE_TYPE_EMU \|\|
			omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
	core_next_state == PWRDM_POWER_OFF)		core_next_state == PWRDM_POWER_OFF)
	sdrc_write_reg(sdrc_pwr, SDRC_POWER);		sdrc_write_reg(sdrc_pwr, SDRC_POWER);

	@@ -455,6 +455,8 @@ void omap_sram_idle(void)
	}		}
	omap3_intc_resume_idle();		omap3_intc_resume_idle();

			pwrdm_post_transition();

	/* PER */		/* PER */
	if (per_next_state < PWRDM_POWER_ON) {		if (per_next_state < PWRDM_POWER_ON) {
	per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);		per_prev_state = pwrdm_read_prev_pwrst(per_pwrdm);
	@@ -475,11 +477,10 @@ void omap_sram_idle(void)
	core_next_state < PWRDM_POWER_ON)) {		core_next_state < PWRDM_POWER_ON)) {
	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
	PM_WKEN);		PM_WKEN);
			if (omap3_has_io_chain_ctrl())
	omap3_disable_io_chain();		omap3_disable_io_chain();
	}		}

	pwrdm_post_transition();

	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);		clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
	}		}

	@@ -870,6 +871,9 @@ static int __init omap3_pm_init(void)
	if (!cpu_is_omap34xx())		if (!cpu_is_omap34xx())
	return -ENODEV;		return -ENODEV;

			if (!omap3_has_io_chain_ctrl())
			pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");

	pm_errata_configure();		pm_errata_configure();

	/* XXX prcm_setup_regs needs to be before enabling hw		/* XXX prcm_setup_regs needs to be before enabling hw

arch/arm/plat-omap/include/plat/cpu.h

+12 −5

Original line number	Original line	Diff line number	Diff line
	@@ -399,6 +399,13 @@ void omap2_check_revision(void);

	/*		/*
	* Runtime detection of OMAP3 features		* Runtime detection of OMAP3 features
			*
			* OMAP3_HAS_IO_CHAIN_CTRL: Some later members of the OMAP3 chip
			* family have OS-level control over the I/O chain clock. This is
			* to avoid a window during which wakeups could potentially be lost
			* during powerdomain transitions. If this bit is set, it
			* indicates that the chip does support OS-level control of this
			* feature.
	*/		*/
	extern u32 omap_features;		extern u32 omap_features;

	@@ -410,9 +417,10 @@ extern u32 omap_features;
	#define OMAP3_HAS_192MHZ_CLK BIT(5)		#define OMAP3_HAS_192MHZ_CLK BIT(5)
	#define OMAP3_HAS_IO_WAKEUP BIT(6)		#define OMAP3_HAS_IO_WAKEUP BIT(6)
	#define OMAP3_HAS_SDRC BIT(7)		#define OMAP3_HAS_SDRC BIT(7)
	#define OMAP4_HAS_MPU_1GHZ BIT(8)		#define OMAP3_HAS_IO_CHAIN_CTRL BIT(8)
	#define OMAP4_HAS_MPU_1_2GHZ BIT(9)		#define OMAP4_HAS_MPU_1GHZ BIT(9)
	#define OMAP4_HAS_MPU_1_5GHZ BIT(10)		#define OMAP4_HAS_MPU_1_2GHZ BIT(10)
			#define OMAP4_HAS_MPU_1_5GHZ BIT(11)


	#define OMAP3_HAS_FEATURE(feat,flag) \		#define OMAP3_HAS_FEATURE(feat,flag) \
	@@ -429,12 +437,11 @@ OMAP3_HAS_FEATURE(isp, ISP)
	OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)		OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
	OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)		OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
	OMAP3_HAS_FEATURE(sdrc, SDRC)		OMAP3_HAS_FEATURE(sdrc, SDRC)
			OMAP3_HAS_FEATURE(io_chain_ctrl, IO_CHAIN_CTRL)

	/*		/*
	* Runtime detection of OMAP4 features		* Runtime detection of OMAP4 features
	*/		*/
	extern u32 omap_features;

	#define OMAP4_HAS_FEATURE(feat, flag) \		#define OMAP4_HAS_FEATURE(feat, flag) \
	static inline unsigned int omap4_has_ ##feat(void) \		static inline unsigned int omap4_has_ ##feat(void) \
	{ \		{ \