Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7fa5e8dc authored by Ashok Vuyyuru's avatar Ashok Vuyyuru
Browse files

msm: ipa4: Update wdi2 channel scratch variable 



Wlan use cases would break according to new wlan data interface
specification, Due to which DUT cannot share internet to any wifi
client or even cannot use internet via wifi.So, update wlan offload
channel's scratch structure in ipa driver, according to new
wlan data interface specification.

Change-Id: Ic085c670d81d6e58b4b91a347338861ecbfb7372
Signed-off-by: default avatarAshok Vuyyuru <avuyyuru@codeaurora.org>
parent a7d847f5

drivers/platform/msm/gsi/gsi.c

+32 −0
Original line number Diff line number Diff line
@@ -2523,6 +2523,38 @@ int gsi_write_channel_scratch3_reg(unsigned long chan_hdl, 
}

EXPORT_SYMBOL(gsi_write_channel_scratch3_reg);



int gsi_write_channel_scratch2_reg(unsigned long chan_hdl,

		union __packed gsi_wdi2_channel_scratch2_reg val)

{

	struct gsi_chan_ctx *ctx;



	if (!gsi_ctx) {

		pr_err("%s:%d gsi context not allocated\n", __func__, __LINE__);

		return -GSI_STATUS_NODEV;

	}



	if (chan_hdl >= gsi_ctx->max_ch) {

		GSIERR("bad params chan_hdl=%lu\n", chan_hdl);

		return -GSI_STATUS_INVALID_PARAMS;

	}



	ctx = &gsi_ctx->chan[chan_hdl];



	mutex_lock(&ctx->mlock);



	ctx->scratch.wdi2_new.endp_metadatareg_offset =

				val.wdi.endp_metadatareg_offset;

	ctx->scratch.wdi2_new.qmap_id = val.wdi.qmap_id;

	val.wdi.update_ri_moderation_threshold =

		ctx->scratch.wdi2_new.update_ri_moderation_threshold;

	gsi_writel(val.data.word1, gsi_ctx->base +

		GSI_EE_n_GSI_CH_k_SCRATCH_2_OFFS(chan_hdl,

			gsi_ctx->per.ee));

	mutex_unlock(&ctx->mlock);

	return GSI_STATUS_SUCCESS;

}

EXPORT_SYMBOL(gsi_write_channel_scratch2_reg);



static void __gsi_read_channel_scratch(unsigned long chan_hdl,

		union __packed gsi_channel_scratch * val)

{

drivers/platform/msm/ipa/ipa_v3/ipa.c

+2 −1
Original line number Diff line number Diff line
@@ -7131,7 +7131,8 @@ int ipa3_get_smmu_params(struct ipa_smmu_in_params *in, 


	switch (in->smmu_client) {

	case IPA_SMMU_WLAN_CLIENT:

		if (ipa3_ctx->ipa_wdi3_over_gsi)

		if (ipa3_ctx->ipa_wdi3_over_gsi ||

			ipa3_ctx->ipa_wdi2_over_gsi)

			is_smmu_enable =

				!(ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_AP] ||

				ipa3_ctx->s1_bypass_arr[IPA_SMMU_CB_WLAN]);

drivers/platform/msm/ipa/ipa_v3/ipa_uc_wdi.c

+58 −24
Original line number Diff line number Diff line
@@ -1099,6 +1099,7 @@ int ipa3_connect_gsi_wdi_pipe(struct ipa_wdi_in_params *in, 
	union __packed gsi_channel_scratch gsi_scratch;

	phys_addr_t pa;

	unsigned long va;

	unsigned long wifi_rx_ri_addr = 0;

	u32 gsi_db_reg_phs_addr_lsb;

	u32 gsi_db_reg_phs_addr_msb;
@@ -1276,16 +1277,11 @@ int ipa3_connect_gsi_wdi_pipe(struct ipa_wdi_in_params *in, 
					NULL,

					4,

					false,

					&va)) {

					&wifi_rx_ri_addr)) {

			IPAERR("fail to create gsi RX rng RP\n");

			result = -ENOMEM;

			goto gsi_timeout;

		}

		gsi_scratch.wdi.wifi_rx_ri_addr_low =

			va & 0xFFFFFFFF;

		gsi_scratch.wdi.wifi_rx_ri_addr_high =

			(va & 0xFFFFF00000000) >> 32;



		len = in->smmu_enabled ?

			in->u.ul_smmu.rdy_comp_ring_size :

			in->u.ul.rdy_comp_ring_size;
@@ -1324,13 +1320,6 @@ int ipa3_connect_gsi_wdi_pipe(struct ipa_wdi_in_params *in, 
			goto gsi_timeout;

		}

		gsi_evt_ring_props.rp_update_addr = va;

		gsi_scratch.wdi.wdi_rx_vdev_id = 0xff;

		gsi_scratch.wdi.wdi_rx_fw_desc = 0xff;

		gsi_scratch.wdi.endp_metadatareg_offset =

					ipahal_get_reg_mn_ofst(

					IPA_ENDP_INIT_HDR_METADATA_n, 0,

							ipa_ep_idx)/4;

		gsi_scratch.wdi.qmap_id = 0;

	}



	ep->valid = 1;
@@ -1388,11 +1377,44 @@ int ipa3_connect_gsi_wdi_pipe(struct ipa_wdi_in_params *in, 


	num_ring_ele = ep->gsi_mem_info.evt_ring_len/gsi_evt_ring_props.re_size;

	IPAERR("UPDATE_RI_MODERATION_THRESHOLD: %d\n", num_ring_ele);

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_7) {

		if (IPA_CLIENT_IS_PROD(in->sys.client)) {

			gsi_scratch.wdi.wifi_rx_ri_addr_low =

				wifi_rx_ri_addr & 0xFFFFFFFF;

			gsi_scratch.wdi.wifi_rx_ri_addr_high =

				(wifi_rx_ri_addr & 0xFFFFF00000000) >> 32;

			gsi_scratch.wdi.wdi_rx_vdev_id = 0xff;

			gsi_scratch.wdi.wdi_rx_fw_desc = 0xff;

			gsi_scratch.wdi.endp_metadatareg_offset =

						ipahal_get_reg_mn_ofst(

						IPA_ENDP_INIT_HDR_METADATA_n, 0,

								ipa_ep_idx)/4;

			gsi_scratch.wdi.qmap_id = 0;

		}

		gsi_scratch.wdi.update_ri_moderation_threshold =

			min(UPDATE_RI_MODERATION_THRESHOLD, num_ring_ele);

		gsi_scratch.wdi.update_ri_moderation_counter = 0;

		gsi_scratch.wdi.wdi_rx_tre_proc_in_progress = 0;

	gsi_scratch.wdi.resv1 = 0;

	} else {

		if (IPA_CLIENT_IS_PROD(in->sys.client)) {

			gsi_scratch.wdi2_new.wifi_rx_ri_addr_low =

				wifi_rx_ri_addr & 0xFFFFFFFF;

			gsi_scratch.wdi2_new.wifi_rx_ri_addr_high =

				(wifi_rx_ri_addr & 0xFFFFF00000000) >> 32;

			gsi_scratch.wdi2_new.wdi_rx_vdev_id = 0xff;

			gsi_scratch.wdi2_new.wdi_rx_fw_desc = 0xff;

			gsi_scratch.wdi2_new.endp_metadatareg_offset =

						ipahal_get_reg_mn_ofst(

						IPA_ENDP_INIT_HDR_METADATA_n, 0,

								ipa_ep_idx)/4;

			gsi_scratch.wdi2_new.qmap_id = 0;

		}

		gsi_scratch.wdi2_new.update_ri_moderation_threshold =

			min(UPDATE_RI_MODERATION_THRESHOLD, num_ring_ele);

		gsi_scratch.wdi2_new.update_ri_moderation_counter = 0;

		gsi_scratch.wdi2_new.wdi_rx_tre_proc_in_progress = 0;

	}



	result = gsi_write_channel_scratch(ep->gsi_chan_hdl,

			gsi_scratch);

	if (result != GSI_STATUS_SUCCESS) {
@@ -2708,17 +2730,29 @@ int ipa3_write_qmapid_gsi_wdi_pipe(u32 clnt_hdl, u8 qmap_id) 
{

	int result = 0;

	struct ipa3_ep_context *ep;

	union __packed gsi_wdi_channel_scratch3_reg gsi_scratch;

	union __packed gsi_wdi_channel_scratch3_reg gsi_scratch3;

	union __packed gsi_wdi2_channel_scratch2_reg gsi_scratch2;



	memset(&gsi_scratch, 0, sizeof(gsi_scratch));

	ep = &ipa3_ctx->ep[clnt_hdl];

	IPA_ACTIVE_CLIENTS_INC_EP(ipa3_get_client_mapping(clnt_hdl));



	gsi_scratch.wdi.qmap_id = qmap_id;

	gsi_scratch.wdi.endp_metadatareg_offset = ipahal_get_reg_mn_ofst(

	if (ipa3_ctx->ipa_hw_type < IPA_HW_v4_7) {

		memset(&gsi_scratch3, 0, sizeof(gsi_scratch3));

		gsi_scratch3.wdi.qmap_id = qmap_id;

		gsi_scratch3.wdi.endp_metadatareg_offset =

			ipahal_get_reg_mn_ofst(

				IPA_ENDP_INIT_HDR_METADATA_n, 0, clnt_hdl)/4;



	result = gsi_write_channel_scratch3_reg(ep->gsi_chan_hdl, gsi_scratch);

		result = gsi_write_channel_scratch3_reg(ep->gsi_chan_hdl,

								gsi_scratch3);

	} else {

		memset(&gsi_scratch2, 0, sizeof(gsi_scratch2));

		gsi_scratch2.wdi.qmap_id = qmap_id;

		gsi_scratch2.wdi.endp_metadatareg_offset =

			ipahal_get_reg_mn_ofst(

				IPA_ENDP_INIT_HDR_METADATA_n, 0, clnt_hdl)/4;

		result = gsi_write_channel_scratch2_reg(ep->gsi_chan_hdl,

								gsi_scratch2);

	}

	if (result != GSI_STATUS_SUCCESS) {

		IPAERR("gsi_write_channel_scratch failed %d\n",

			result);

include/linux/msm_gsi.h

+112 −0
Original line number Diff line number Diff line
@@ -702,6 +702,74 @@ struct __packed gsi_wdi_channel_scratch { 
	uint32_t wdi_rx_qmap_id_internal:16;

};



/**

 * gsi_wdi2_channel_scratch_lito - WDI protocol SW config area of

 * channel scratch

 *

 * @wifi_rx_ri_addr_low: Low 32 bits of Transfer ring Read Index address.

 * @wifi_rx_ri_addr_high: High 32 bits of Transfer ring Read Index address.

 * @update_ri_moderation_threshold: Threshold N for Transfer ring Read Index

 *                                  N is the number of packets that IPA will

 *                                  process before Wifi transfer ring Ri will

 *                                  be updated.

 * @qmap_id: Rx only, used for setting metadata register in IPA. Read only field

 *           for MCS. Write for SW.

 * @endp_metadatareg_offset: Rx only, the offset of IPA_ENDP_INIT_HDR_METADATA

 *                           of the corresponding endpoint in 4B words from IPA

 *                           base address. Read only field for MCS.

 *                           Write for SW.

 * @wdi_rx_vdev_id: Rx only. Initialized to 0xFF by SW after allocating channel

 *                  and before starting it. Both FW_DESC and VDEV_ID are part

 *                  of a scratch word that is Read/Write for both MCS and SW.

 *                  To avoid race conditions, SW should not update this field

 *                  after starting the channel.

 * @wdi_rx_fw_desc: Rx only. Initialized to 0xFF by SW after allocating channel

 *                  and before starting it. After Start, this is a Read only

 *                  field for SW.

 * @update_ri_moderation_counter: This field is incremented with each TRE

 *                                processed in MCS.

 * @wdi_rx_tre_proc_in_progress: It is set if IPA IF returned BECAME FULL

 *                               status after MCS submitted an inline immediate

 *                               command to update the metadata. It allows MCS

 *                               to know that it has to retry sending the TRE

 *                               to IPA.

 * @outstanding_tlvs_counter: It is the count of outstanding TLVs submitted to

 *                           IPA by MCS and waiting for AOS completion from IPA.

 * @wdi_rx_pkt_length: If WDI_RX_TRE_PROC_IN_PROGRESS is set, this field is

 *                     valid and contains the packet length of the TRE that

 *                     needs to be submitted to IPA.

 * @resv1: reserved bits.

 * @pkt_comp_count: It is incremented on each AOS received. When event ring

 *                  Write index is updated, it is decremented by the same

 *                  amount.

 * @stop_in_progress_stm: If a Stop request is in progress, this will indicate

 *                        the current stage of processing of the stop within MCS

 * @resv2: reserved bits.

 * wdi_rx_qmap_id_internal: Initialized to 0 by MCS when the channel is

 *                          allocated. It is updated to the current value of SW

 *                          QMAP ID that is being written by MCS to the IPA

 *                          metadata register.

 */

struct __packed gsi_wdi2_channel_scratch_new {

	uint32_t wifi_rx_ri_addr_low;

	uint32_t wifi_rx_ri_addr_high;

	uint32_t update_ri_moderation_threshold:5;

	uint32_t qmap_id:8;

	uint32_t resv1:3;

	uint32_t endp_metadatareg_offset:16;

	uint32_t wdi_rx_vdev_id:8;

	uint32_t wdi_rx_fw_desc:8;

	uint32_t update_ri_moderation_counter:6;

	uint32_t wdi_rx_tre_proc_in_progress:1;

	uint32_t resv4:1;

	uint32_t outstanding_tlvs_counter:8;

	uint32_t wdi_rx_pkt_length:16;

	uint32_t resv2:2;

	uint32_t pkt_comp_count:11;

	uint32_t stop_in_progress_stm:3;

	uint32_t resv3:16;

	uint32_t wdi_rx_qmap_id_internal:16;

};

/**

* gsi_mhip_channel_scratch - MHI PRIME protocol SW config area of

* channel scratch
@@ -805,6 +873,7 @@ union __packed gsi_channel_scratch { 
	struct __packed gsi_11ad_tx_channel_scratch tx_11ad;

	struct __packed gsi_wdi3_channel_scratch wdi3;

	struct __packed gsi_mhip_channel_scratch mhip;

	struct __packed gsi_wdi2_channel_scratch_new wdi2_new;

	struct __packed {

		uint32_t word1;

		uint32_t word2;
@@ -835,6 +904,30 @@ union __packed gsi_wdi_channel_scratch3_reg { 
	} data;

};



/**

 * gsi_wdi2_channel_scratch2 - WDI protocol SW config area of

 * channel scratch2

 */



struct __packed gsi_wdi2_channel_scratch2 {

	uint32_t update_ri_moderation_threshold:5;

	uint32_t qmap_id:8;

	uint32_t resv1:3;

	uint32_t endp_metadatareg_offset:16;

};



/**

 * gsi_wdi_channel_scratch2_reg - channel scratch2 SW config area

 *

 */



union __packed gsi_wdi2_channel_scratch2_reg {

	struct __packed gsi_wdi2_channel_scratch2 wdi;

	struct __packed {

		uint32_t word1;

	} data;

};



/**

 * gsi_mhi_evt_scratch - MHI protocol SW config area of

 * event scratch
@@ -1192,6 +1285,19 @@ int gsi_write_channel_scratch(unsigned long chan_hdl, 
int gsi_write_channel_scratch3_reg(unsigned long chan_hdl,

		union __packed gsi_wdi_channel_scratch3_reg val);



/**

 * gsi_write_channel_scratch2_reg - Peripheral should call this function to

 * write to the scratch2 reg area of the channel context

 *

 * @chan_hdl:  Client handle previously obtained from

 *             gsi_alloc_channel

 * @val:       Value to write

 *

 * @Return gsi_status

 */

int gsi_write_channel_scratch2_reg(unsigned long chan_hdl,

		union __packed gsi_wdi2_channel_scratch2_reg val);



/**

 * gsi_read_channel_scratch - Peripheral should call this function to

 * read to the scratch area of the channel context
@@ -1653,6 +1759,12 @@ static inline int gsi_write_channel_scratch3_reg(unsigned long chan_hdl, 
	return -GSI_STATUS_UNSUPPORTED_OP;

}



static inline int gsi_write_channel_scratch2_reg(unsigned long chan_hdl,

		union __packed gsi_wdi2_channel_scratch2_reg val)

{

	return -GSI_STATUS_UNSUPPORTED_OP;

}



static inline int gsi_read_channel_scratch(unsigned long chan_hdl,

		union __packed gsi_channel_scratch *val)

{