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Commit 7f62e501 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: add support for GLC, FCHE and MHUB perfcounters"

parents e07928ab e50ac814

drivers/gpu/msm/a6xx_reg.h

+48 −0
Original line number Diff line number Diff line
@@ -391,6 +391,38 @@ 
#define A6XX_RBBM_PERFCTR_RBBM_SEL_2             0x509

#define A6XX_RBBM_PERFCTR_RBBM_SEL_3             0x50A

#define A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED        0x50B

#define A6XX_RBBM_PERFCTR_MHUB_0_LO              0x512

#define A6XX_RBBM_PERFCTR_MHUB_0_HI              0x513

#define A6XX_RBBM_PERFCTR_MHUB_1_LO              0x514

#define A6XX_RBBM_PERFCTR_MHUB_1_HI              0x515

#define A6XX_RBBM_PERFCTR_MHUB_2_LO              0x516

#define A6XX_RBBM_PERFCTR_MHUB_2_HI              0x517

#define A6XX_RBBM_PERFCTR_MHUB_3_LO              0x518

#define A6XX_RBBM_PERFCTR_MHUB_3_HI              0x519

#define A6XX_RBBM_PERFCTR_FCHE_0_LO              0x51A

#define A6XX_RBBM_PERFCTR_FCHE_0_HI              0x51B

#define A6XX_RBBM_PERFCTR_FCHE_1_LO              0x51C

#define A6XX_RBBM_PERFCTR_FCHE_1_HI              0x51D

#define A6XX_RBBM_PERFCTR_FCHE_2_LO              0x51E

#define A6XX_RBBM_PERFCTR_FCHE_2_HI              0x51F

#define A6XX_RBBM_PERFCTR_FCHE_3_LO              0x520

#define A6XX_RBBM_PERFCTR_FCHE_3_HI              0x521

#define A6XX_RBBM_PERFCTR_GLC_0_LO               0x522

#define A6XX_RBBM_PERFCTR_GLC_0_HI               0x523

#define A6XX_RBBM_PERFCTR_GLC_1_LO               0x524

#define A6XX_RBBM_PERFCTR_GLC_1_HI               0x525

#define A6XX_RBBM_PERFCTR_GLC_2_LO               0x526

#define A6XX_RBBM_PERFCTR_GLC_2_HI               0x527

#define A6XX_RBBM_PERFCTR_GLC_3_LO               0x528

#define A6XX_RBBM_PERFCTR_GLC_3_HI               0x529

#define A6XX_RBBM_PERFCTR_GLC_4_LO               0x52A

#define A6XX_RBBM_PERFCTR_GLC_4_HI               0x52B

#define A6XX_RBBM_PERFCTR_GLC_5_LO               0x52C

#define A6XX_RBBM_PERFCTR_GLC_5_HI               0x52D

#define A6XX_RBBM_PERFCTR_GLC_6_LO               0x52E

#define A6XX_RBBM_PERFCTR_GLC_6_HI               0x52F

#define A6XX_RBBM_PERFCTR_GLC_7_LO               0x530

#define A6XX_RBBM_PERFCTR_GLC_7_HI               0x531



#define A6XX_RBBM_ISDB_CNT                       0x533

#define A6XX_RBBM_NC_MODE_CNTL                   0X534
@@ -655,6 +687,22 @@ 
#define A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST  0x8E3B

#define A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD    0x8E3D

#define A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x8E50

#define A6XX_RB_PERFCTR_GLC_SEL_0            0x8E90

#define A6XX_RB_PERFCTR_GLC_SEL_1            0x8E91

#define A6XX_RB_PERFCTR_GLC_SEL_2            0x8E92

#define A6XX_RB_PERFCTR_GLC_SEL_3            0x8E93

#define A6XX_RB_PERFCTR_GLC_SEL_4            0x8E94

#define A6XX_RB_PERFCTR_GLC_SEL_5            0x8E95

#define A6XX_RB_PERFCTR_GLC_SEL_6            0x8E96

#define A6XX_RB_PERFCTR_GLC_SEL_7            0x8E97

#define A6XX_RB_PERFCTR_MHUB_SEL_0           0x8EA0

#define A6XX_RB_PERFCTR_MHUB_SEL_1           0x8EA1

#define A6XX_RB_PERFCTR_MHUB_SEL_2           0x8EA2

#define A6XX_RB_PERFCTR_MHUB_SEL_3           0x8EA3

#define A6XX_RB_PERFCTR_FCHE_SEL_0           0x8EB0

#define A6XX_RB_PERFCTR_FCHE_SEL_1           0x8EB1

#define A6XX_RB_PERFCTR_FCHE_SEL_2           0x8EB2

#define A6XX_RB_PERFCTR_FCHE_SEL_3           0x8EB3



/* PC registers */

#define A6XX_PC_DBG_ECO_CNTL                0x9E00

drivers/gpu/msm/adreno_a6xx.c

+58 −0
Original line number Diff line number Diff line
@@ -2210,6 +2210,47 @@ static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = { 
		A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 },

};



static struct adreno_perfcount_register a6xx_perfcounters_glc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_0_LO,

		A6XX_RBBM_PERFCTR_GLC_0_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_1_LO,

		A6XX_RBBM_PERFCTR_GLC_1_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_2_LO,

		A6XX_RBBM_PERFCTR_GLC_2_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_2 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_3_LO,

		A6XX_RBBM_PERFCTR_GLC_3_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_3 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_4_LO,

		A6XX_RBBM_PERFCTR_GLC_4_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_4 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_5_LO,

		A6XX_RBBM_PERFCTR_GLC_5_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_5 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_6_LO,

		A6XX_RBBM_PERFCTR_GLC_6_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_6 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_GLC_7_LO,

		A6XX_RBBM_PERFCTR_GLC_7_HI, -1, A6XX_RB_PERFCTR_GLC_SEL_7 },

};



static struct adreno_perfcount_register a6xx_perfcounters_fche[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_FCHE_0_LO,

		A6XX_RBBM_PERFCTR_FCHE_0_HI, -1, A6XX_RB_PERFCTR_FCHE_SEL_0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_FCHE_1_LO,

		A6XX_RBBM_PERFCTR_FCHE_1_HI, -1, A6XX_RB_PERFCTR_FCHE_SEL_1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_FCHE_2_LO,

		A6XX_RBBM_PERFCTR_FCHE_2_HI, -1, A6XX_RB_PERFCTR_FCHE_SEL_2 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_FCHE_3_LO,

		A6XX_RBBM_PERFCTR_FCHE_3_HI, -1, A6XX_RB_PERFCTR_FCHE_SEL_3 },

};



static struct adreno_perfcount_register a6xx_perfcounters_mhub[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_MHUB_0_LO,

		A6XX_RBBM_PERFCTR_MHUB_0_HI, -1, A6XX_RB_PERFCTR_MHUB_SEL_0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_MHUB_1_LO,

		A6XX_RBBM_PERFCTR_MHUB_1_HI, -1, A6XX_RB_PERFCTR_MHUB_SEL_1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_MHUB_2_LO,

		A6XX_RBBM_PERFCTR_MHUB_2_HI, -1, A6XX_RB_PERFCTR_MHUB_SEL_2 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_MHUB_3_LO,

		A6XX_RBBM_PERFCTR_MHUB_3_HI, -1, A6XX_RB_PERFCTR_MHUB_SEL_3 },

};



/*

 * ADRENO_PERFCOUNTER_GROUP_RESTORE flag is enabled by default

 * because most of the perfcounter groups need to be restored
@@ -2316,6 +2357,23 @@ static void a6xx_platform_setup(struct adreno_device *adreno_dev) 
		gpudev->vbif_xin_halt_ctrl0_mask =

				A6XX_VBIF_XIN_HALT_CTRL0_MASK;



	if (adreno_is_a702(adreno_dev)) {

		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_GLC].regs =

				a6xx_perfcounters_glc;

		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_GLC].reg_count

				= ARRAY_SIZE(a6xx_perfcounters_glc);



		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_FCHE].regs =

				a6xx_perfcounters_fche;

		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_FCHE].reg_count

				= ARRAY_SIZE(a6xx_perfcounters_fche);



		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_MHUB].regs =

				a6xx_perfcounters_mhub;

		a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_MHUB].reg_count

				= ARRAY_SIZE(a6xx_perfcounters_mhub);

	}



	/* Set the GPU busy counter for frequency scaling */

	adreno_dev->perfctr_pwr_lo = A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L;

drivers/gpu/msm/adreno_perfcounter.c

+7 −1
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2002,2007-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2002,2007-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/slab.h>
@@ -126,6 +126,9 @@ void adreno_perfcounter_restore(struct adreno_device *adreno_dev) 
	struct adreno_perfcount_group *group;

	unsigned int counter, groupid;



	if (adreno_is_a702(adreno_dev))

		return;



	if (counters == NULL)

		return;
@@ -159,6 +162,9 @@ inline void adreno_perfcounter_save(struct adreno_device *adreno_dev) 
	struct adreno_perfcount_group *group;

	unsigned int counter, groupid;



	if (adreno_is_a702(adreno_dev))

		return;



	if (counters == NULL)

		return;

include/uapi/linux/msm_kgsl.h

+5 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */

/*

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _UAPI_MSM_KGSL_H
@@ -462,7 +462,10 @@ struct kgsl_context_property_fault { 
#define KGSL_PERFCOUNTER_GROUP_CP_PWR 0x21

#define KGSL_PERFCOUNTER_GROUP_GPMU_PWR 0x22

#define KGSL_PERFCOUNTER_GROUP_ALWAYSON_PWR 0x23

#define KGSL_PERFCOUNTER_GROUP_MAX 0x24

#define KGSL_PERFCOUNTER_GROUP_GLC 0x24

#define KGSL_PERFCOUNTER_GROUP_FCHE 0x25

#define KGSL_PERFCOUNTER_GROUP_MHUB 0x26

#define KGSL_PERFCOUNTER_GROUP_MAX 0x27



#define KGSL_PERFCOUNTER_NOT_USED 0xFFFFFFFF

#define KGSL_PERFCOUNTER_BROKEN 0xFFFFFFFE