Commit 7f1052a8 authored Apr 26, 2016 by Ville Syrjälä

drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequency



Update CDCLK_FREQ on BDW after changing the cdclk frequency. Not sure
if this is a late addition to the spec, or if I simply overlooked this
step when writing the original code.

This is what Bspec has to say about CDCLK_FREQ:
"Program this field to the CD clock frequency minus one. This is used to
 generate a divided down clock for miscellaneous timers in display."

And the "Broadwell Sequences for Changing CD Clock Frequency" section
clarifies this further:
"For CD clock 337.5 MHz, program 337 decimal.
 For CD clock 450 MHz, program 449 decimal.
 For CD clock 540 MHz, program 539 decimal.
 For CD clock 675 MHz, program 674 decimal."

Cc: stable@vger.kernel.org
Cc: Mika Kahola <mika.kahola@intel.com>
Fixes: b432e5cf ("drm/i915: BDW clock change support")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1461689194-6079-2-git-send-email-ville.syrjala@linux.intel.com


Reviewed-by: Mika Kahola <mika.kahola@intel.com>

parent 042ab0c3

drivers/gpu/drm/i915/i915_reg.h

+2 −0

Original line number	Diff line number	Diff line
		@@ -7518,6 +7518,8 @@ enum skl_disp_power_wells {
		#define TRANS_CLK_SEL_DISABLED (0x0<<29)
		#define TRANS_CLK_SEL_PORT(x) (((x)+1)<<29)

		#define CDCLK_FREQ _MMIO(0x46200)

		#define _TRANSA_MSA_MISC 0x60410
		#define _TRANSB_MSA_MISC 0x61410
		#define _TRANSC_MSA_MISC 0x62410

drivers/gpu/drm/i915/intel_display.c

+2 −0

Original line number	Diff line number	Diff line
		@@ -9682,6 +9682,8 @@ static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
		sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
		mutex_unlock(&dev_priv->rps.hw_lock);

		I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);

		intel_update_cdclk(dev);

		WARN(cdclk != dev_priv->cdclk_freq,