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Commit 7f0b61ad authored by Caesar Wang's avatar Caesar Wang Committed by Heiko Stuebner
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ARM: rockchip: fix the SMP code style 



Use the below scripts to check:
scripts/checkpatch.pl -f --subject arch/arm/mach-rockchip/platsmp.c

Signed-off-by: default avatarCaesar Wang <wxt@rock-chips.com>
Reviewed-by: default avatarDouglas Anderson <dianders@chromium.org>
Reviewed-by: default avatarKever Yang <kever.yang@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent e306bc16

arch/arm/mach-rockchip/platsmp.c

+8 −6
Original line number Diff line number Diff line
@@ -139,7 +139,8 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) 
		return ret;



	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {

		/* We communicate with the bootrom to active the cpus other

		/*

		 * We communicate with the bootrom to active the cpus other

		 * than cpu0, after a blob of initialize code, they will

		 * stay at wfe state, once they are actived, they will check

		 * the mailbox:
@@ -148,7 +149,7 @@ static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle) 
		 * The cpu0 need to wait the other cpus other than cpu0 entering

		 * the wfe state.The wait time is affected by many aspects.

		 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)

		 * */

		 */

		mdelay(1); /* ensure the cpus other than cpu0 to startup */



		writel(virt_to_phys(rockchip_secondary_startup),
@@ -348,4 +349,5 @@ static struct smp_operations rockchip_smp_ops __initdata = { 
	.cpu_die		= rockchip_cpu_die,

#endif

};



CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);