Commit 7f02f18e authored May 25, 2018 by Sekhar Nori Committed by Michael Turquette May 30, 2018

clk: davinci: pll-dm646x: keep PLL2 SYSCLK1 always enabled



PLL2 SYSCLK1 on DM646x is connected to DDR2 PHY and cannot
be disabled. Mark it so to prevent unused clock disable
infrastructure from disabling it.

Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Reviewed-by: David Lechner <david@lechnology.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/20180525181150.17873-5-david@lechnology.com

parent 715478bb

drivers/clk/davinci/pll-dm646x.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -72,7 +72,7 @@ static const struct davinci_pll_clk_info dm646x_pll2_info = {
		.flags = 0,
		};

		SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
		SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, SYSCLK_ALWAYS_ENABLED);

		int dm646x_pll2_init(struct device dev, void __iomem base)
		{