Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7ef69843 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amdgpu: fix memory clock can't switch on CI. 



if we set only lowest mclk level enabled,
when we enable uvd dpm during boot time,
mclk will be fixed in the lowest level.
the mclk switch will fail if try to enable
other level of mclk at this time.
so set all mclk levels enabled.

Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent fb82afab

drivers/gpu/drm/amd/amdgpu/ci_dpm.c

+1 −2
Original line number Diff line number Diff line
@@ -3036,6 +3036,7 @@ static int ci_populate_single_memory_level(struct amdgpu_device *adev, 
						      memory_clock,

						      &memory_level->MinVddcPhases);



	memory_level->EnabledForActivity = 1;

	memory_level->EnabledForThrottle = 1;

	memory_level->UpH = 0;

	memory_level->DownH = 100;
@@ -3468,8 +3469,6 @@ static int ci_populate_all_memory_levels(struct amdgpu_device *adev) 
			return ret;

	}



	pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1;



	if ((dpm_table->mclk_table.count >= 2) &&

	    ((adev->pdev->device == 0x67B0) || (adev->pdev->device == 0x67B1))) {

		pi->smc_state_table.MemoryLevel[1].MinVddc =