Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7eac928c authored by Quan Nguyen's avatar Quan Nguyen Committed by David S. Miller
Browse files

drivers: net: xgene: Add workaround for errata 10GE_1 



This patch implements workaround for errata 10GE_1:
10Gb Ethernet port FIFO threshold default values are incorrect.

Signed-off-by: default avatarQuan Nguyen <qnguyen@apm.com>
Signed-off-by: default avatarToan Le <toanle@apm.com>
Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Tested-by: default avatarFushen Chen <fchen@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0a0400c3

drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c

+7 −0
Original line number Diff line number Diff line
@@ -341,8 +341,15 @@ static void xgene_xgmac_init(struct xgene_enet_pdata *pdata) 


	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data);

	data |= CFG_RSIF_FPBUFF_TIMEOUT_EN;

	/* Errata 10GE_1 - FIFO threshold default value incorrect */

	RSIF_CLE_BUFF_THRESH_SET(&data, XG_RSIF_CLE_BUFF_THRESH);

	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data);



	/* Errata 10GE_1 - FIFO threshold default value incorrect */

	xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, &data);

	RSIF_PLC_CLE_BUFF_THRESH_SET(&data, XG_RSIF_PLC_CLE_BUFF_THRESH);

	xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG1_REG_ADDR, data);



	xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data);

	data |= BIT(12);

	xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data);

drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.h

+5 −0
Original line number Diff line number Diff line
@@ -65,6 +65,11 @@ 
#define XG_DEF_PAUSE_THRES		0x390

#define XG_DEF_PAUSE_OFF_THRES		0x2c0

#define XG_RSIF_CONFIG_REG_ADDR		0x00a0

#define XG_RSIF_CLE_BUFF_THRESH                0x3

#define RSIF_CLE_BUFF_THRESH_SET(dst, val)     xgene_set_bits(dst, val, 0, 3)

#define XG_RSIF_CONFIG1_REG_ADDR       0x00b8

#define XG_RSIF_PLC_CLE_BUFF_THRESH    0x1

#define RSIF_PLC_CLE_BUFF_THRESH_SET(dst, val) xgene_set_bits(dst, val, 0, 2)

#define XCLE_BYPASS_REG0_ADDR           0x0160

#define XCLE_BYPASS_REG1_ADDR           0x0164

#define XG_CFG_BYPASS_ADDR		0x0204