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Commit 7e148070 authored by Nishanth Menon's avatar Nishanth Menon Committed by Tero Kristo
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ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies 



OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle
Correction(DCC) to operate safely at frequencies >= 1.4GHz.

Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides
this support.

Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent b4be0189

arch/arm/boot/dts/dra7xx-clocks.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -277,7 +277,7 @@ 


	dpll_mpu_ck: dpll_mpu_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		compatible = "ti,omap5-mpu-dpll-clock";

		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;

		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;

	};

arch/arm/boot/dts/omap54xx-clocks.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -362,7 +362,7 @@ 


	dpll_mpu_ck: dpll_mpu_ck {

		#clock-cells = <0>;

		compatible = "ti,omap4-dpll-clock";

		compatible = "ti,omap5-mpu-dpll-clock";

		clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;

		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;

	};