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Commit 7df5080b authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
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drm/i915: set proper DPIO post divider for VGA on VLV v4 



Supposedly we should use the DAC divider for <300MHz pixel clocks, but as
that doesn't actually work as well as the high freq divider here in
practice, just use the high freq divider all the time.

v2: remove unconditional write (Jesse)
    check for pixel rate properly (Jesse)
v3: give up, the DAC divider apparently doesn't work, and low res modes
    work ok (Jesse)
    remove debug msg (Jesse)

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: default avatarKenneth Graunke <kenneth@whitecape.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 0ef37f3f

drivers/gpu/drm/i915/intel_display.c

+7 −4
Original line number Diff line number Diff line
@@ -4468,9 +4468,12 @@ static void vlv_update_pll(struct intel_crtc *crtc) 
	mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));

	mdiv |= ((bestn << DPIO_N_SHIFT));

	mdiv |= (1 << DPIO_K_SHIFT);

	if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||

	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||

	    intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))



	/*

	 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,

	 * but we don't support that).

	 * Note: don't use the DAC post divider as it seems unstable.

	 */

	mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);

	intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);