Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7de544fd authored by Peter Ujfalusi's avatar Peter Ujfalusi Committed by Mark Brown
Browse files

ASoC: tas2552: Correct CFG1 register bit definitions



Remove the _MASK postfix of the bit definitions, collect the CFG1 bit
definition in one place and correct the bit shifts at the same time.

Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 89683fde
Loading
Loading
Loading
Loading
+7 −7
Original line number Original line Diff line number Diff line
@@ -126,10 +126,10 @@ static void tas2552_sw_shutdown(struct tas2552_data *tas_data, int sw_shutdown)
	if (sw_shutdown)
	if (sw_shutdown)
		cfg1_reg = 0;
		cfg1_reg = 0;
	else
	else
		cfg1_reg = TAS2552_SWS_MASK;
		cfg1_reg = TAS2552_SWS;


	snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1,
	snd_soc_update_bits(tas_data->codec, TAS2552_CFG_1, TAS2552_SWS,
						 TAS2552_SWS_MASK, cfg1_reg);
			    cfg1_reg);
}
}
#endif
#endif


@@ -258,11 +258,11 @@ static int tas2552_mute(struct snd_soc_dai *dai, int mute)
	struct snd_soc_codec *codec = dai->codec;
	struct snd_soc_codec *codec = dai->codec;


	if (mute)
	if (mute)
		cfg1_reg = TAS2552_MUTE_MASK;
		cfg1_reg = TAS2552_MUTE;
	else
	else
		cfg1_reg = ~TAS2552_MUTE_MASK;
		cfg1_reg = ~TAS2552_MUTE;


	snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE_MASK, cfg1_reg);
	snd_soc_update_bits(codec, TAS2552_CFG_1, TAS2552_MUTE, cfg1_reg);


	return 0;
	return 0;
}
}
@@ -370,7 +370,7 @@ static int tas2552_codec_probe(struct snd_soc_codec *codec)
		goto probe_fail;
		goto probe_fail;
	}
	}


	snd_soc_write(codec, TAS2552_CFG_1, TAS2552_MUTE_MASK |
	snd_soc_write(codec, TAS2552_CFG_1, TAS2552_MUTE |
				TAS2552_PLL_SRC_BCLK);
				TAS2552_PLL_SRC_BCLK);
	snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
	snd_soc_write(codec, TAS2552_CFG_3, TAS2552_I2S_OUT_SEL |
				TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);
				TAS2552_DIN_SRC_SEL_AVG_L_R | TAS2552_88_96KHZ);
+8 −9
Original line number Original line Diff line number Diff line
@@ -45,10 +45,14 @@
#define TAS2552_MAX_REG			0x20
#define TAS2552_MAX_REG			0x20


/* CFG1 Register Masks */
/* CFG1 Register Masks */
#define TAS2552_MUTE_MASK		(1 << 2)
#define TAS2552_DEV_RESET		(1 << 0)
#define TAS2552_SWS_MASK		(1 << 1)
#define TAS2552_SWS			(1 << 1)
#define TAS2552_WCLK_MASK		0x07
#define TAS2552_MUTE			(1 << 2)
#define TAS2552_CLASSD_EN_MASK	(1 << 7)
#define TAS2552_PLL_SRC_MCLK		(0x0 << 4)
#define TAS2552_PLL_SRC_BCLK		(0x1 << 4)
#define TAS2552_PLL_SRC_IVCLKIN		(0x2 << 4)
#define TAS2552_PLL_SRC_1_8_FIXED 	(0x3 << 4)
#define TAS2552_PLL_SRC_MASK	 	TAS2552_PLL_SRC_1_8_FIXED


/* CFG2 Register Masks */
/* CFG2 Register Masks */
#define TAS2552_CLASSD_EN		(1 << 7)
#define TAS2552_CLASSD_EN		(1 << 7)
@@ -68,11 +72,6 @@
#define TAS2552_DAIFMT_RIGHT_J		(1 << 4)
#define TAS2552_DAIFMT_RIGHT_J		(1 << 4)
#define TAS2552_DAIFMT_LEFT_J		(0x11 << 3)
#define TAS2552_DAIFMT_LEFT_J		(0x11 << 3)


#define TAS2552_PLL_SRC_MCLK	0x00
#define TAS2552_PLL_SRC_BCLK	(1 << 3)
#define TAS2552_PLL_SRC_IVCLKIN	(1 << 4)
#define TAS2552_PLL_SRC_1_8_FIXED (0x11 << 3)

#define TAS2552_DIN_SRC_SEL_MUTED	0x00
#define TAS2552_DIN_SRC_SEL_MUTED	0x00
#define TAS2552_DIN_SRC_SEL_LEFT	(1 << 4)
#define TAS2552_DIN_SRC_SEL_LEFT	(1 << 4)
#define TAS2552_DIN_SRC_SEL_RIGHT	(1 << 5)
#define TAS2552_DIN_SRC_SEL_RIGHT	(1 << 5)