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Commit 7dbc7f5f authored by Jernej Škrabec's avatar Jernej Škrabec Committed by Chen-Yu Tsai
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clk: sunxi-ng: a83t: Add M divider to TCON1 clock 



TCON1 also has M divider, contrary to TCON0. And the mux is only
2 bits wide, instead of 3.

Fixes: 05359be1 ("clk: sunxi-ng: Add driver for A83T CCU")
Signed-off-by: default avatarJernej Skrabec <jernej.skrabec@siol.net>
[wens@csie.org: Add description about mux width difference]
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
parent cf4881c1

drivers/clk/sunxi-ng/ccu-sun8i-a83t.c

+2 −2
Original line number Diff line number Diff line
@@ -504,8 +504,8 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents, 
				 0x118, 24, 3, BIT(31), CLK_SET_RATE_PARENT);



static const char * const tcon1_parents[] = { "pll-video1" };

static SUNXI_CCU_MUX_WITH_GATE(tcon1_clk, "tcon1", tcon1_parents,

				 0x11c, 24, 3, BIT(31), CLK_SET_RATE_PARENT);

static SUNXI_CCU_M_WITH_MUX_GATE(tcon1_clk, "tcon1", tcon1_parents,

				 0x11c, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(csi_misc_clk, "csi-misc", "osc24M", 0x130, BIT(16), 0);