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Commit 7d955656 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-intel-next-fixes-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel 



Pull i916 drm fixes from Rodrigo Vivi:
 "Since Dave is on paternity leave we are sending drm/i915 fixes for
  v4.14-rc1 directly to you as he had asked us to do.

  The most critical ones are the GPU reset fix for gen2-4 and GVT fix
  for a regression that is blocking gvt init to work on your tree.

  The rest is general fixes for patches coming from drm-next"

Acked-by: default avatarDave Airlie <airlied@redhat.com>

* tag 'drm-intel-next-fixes-2017-09-07' of git://anongit.freedesktop.org/git/drm-intel:
  drm/i915: Re-enable GTT following a device reset
  drm/i915: Annotate user relocs with __user
  drm/i915: Silence sparse by using gfp_t
  drm/i915: Add __rcu to radix tree slot pointer
  drm/i915: Fix the missing PPAT cache attributes on CNL
  drm/i915/gvt: Remove one duplicated MMIO
  drm/i915: Fix enum pipe vs. enum transcoder for the PCH transcoder
  drm/i915: Make i2c lock ops static
  drm/i915: Make i9xx_load_ycbcr_conversion_matrix() static
  drm/i915/edp: Increase T12 panel delay to 900 ms to fix DP AUX CH timeouts
  drm/i915: Ignore duplicate VMA stored within the per-object handle LUT
  drm/i915: Skip fence alignemnt check for the CCS plane
  drm/i915: Treat fb->offsets[] as a raw byte offset instead of a linear offset
  drm/i915: Always wake the device to flush the GTT
  drm/i915: Recreate vmapping even when the object is pinned
  drm/i915: Quietly cancel FBC activation if CRTC is turned off before worker
parents 5f9cc570 426ca2cb

drivers/gpu/drm/i915/gvt/handlers.c

+0 −1
Original line number Diff line number Diff line
@@ -2659,7 +2659,6 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) 
	MMIO_D(HSW_PWR_WELL_CTL_BIOS(SKL_DISP_PW_MISC_IO), D_SKL_PLUS);

	MMIO_DH(HSW_PWR_WELL_CTL_DRIVER(SKL_DISP_PW_MISC_IO), D_SKL_PLUS, NULL,

		skl_power_well_ctl_write);

	MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL_PLUS, NULL, mailbox_write);



	MMIO_D(0xa210, D_SKL_PLUS);

	MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);

drivers/gpu/drm/i915/i915_cmd_parser.c

+1 −1
Original line number Diff line number Diff line
@@ -1073,7 +1073,7 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj, 
		goto unpin_src;

	}



	dst = i915_gem_object_pin_map(dst_obj, I915_MAP_WB);

	dst = i915_gem_object_pin_map(dst_obj, I915_MAP_FORCE_WB);

	if (IS_ERR(dst))

		goto unpin_dst;

drivers/gpu/drm/i915/i915_drv.c

+9 −3
Original line number Diff line number Diff line
@@ -1891,9 +1891,15 @@ void i915_reset(struct drm_i915_private *i915, unsigned int flags) 


	/*

	 * Everything depends on having the GTT running, so we need to start

	 * there.  Fortunately we don't need to do this unless we reset the

	 * chip at a PCI level.

	 *

	 * there.

	 */

	ret = i915_ggtt_enable_hw(i915);

	if (ret) {

		DRM_ERROR("Failed to re-enable GGTT following reset %d\n", ret);

		goto error;

	}



	/*

	 * Next we need to restore the context, but we don't use those

	 * yet either...

	 *

drivers/gpu/drm/i915/i915_drv.h

+3 −0
Original line number Diff line number Diff line
@@ -3479,6 +3479,9 @@ void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); 
enum i915_map_type {

	I915_MAP_WB = 0,

	I915_MAP_WC,

#define I915_MAP_OVERRIDE BIT(31)

	I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,

	I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,

};



/**

drivers/gpu/drm/i915/i915_gem.c

+19 −9
Original line number Diff line number Diff line
@@ -695,13 +695,12 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) 
	switch (obj->base.write_domain) {

	case I915_GEM_DOMAIN_GTT:

		if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {

			if (intel_runtime_pm_get_if_in_use(dev_priv)) {

			intel_runtime_pm_get(dev_priv);

			spin_lock_irq(&dev_priv->uncore.lock);

			POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));

			spin_unlock_irq(&dev_priv->uncore.lock);

			intel_runtime_pm_put(dev_priv);

		}

		}



		intel_fb_obj_flush(obj,

				   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
@@ -2213,7 +2212,7 @@ i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, 
static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj)

{

	struct radix_tree_iter iter;

	void **slot;

	void __rcu **slot;



	radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0)

		radix_tree_delete(&obj->mm.get_page.radix, iter.index);
@@ -2553,6 +2552,9 @@ static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, 
	GEM_BUG_ON(i != n_pages);



	switch (type) {

	default:

		MISSING_CASE(type);

		/* fallthrough to use PAGE_KERNEL anyway */

	case I915_MAP_WB:

		pgprot = PAGE_KERNEL;

		break;
@@ -2583,7 +2585,9 @@ void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, 
	if (ret)

		return ERR_PTR(ret);



	pinned = true;

	pinned = !(type & I915_MAP_OVERRIDE);

	type &= ~I915_MAP_OVERRIDE;



	if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) {

		if (unlikely(IS_ERR_OR_NULL(obj->mm.pages))) {

			ret = ____i915_gem_object_get_pages(obj);
@@ -3258,7 +3262,13 @@ void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) 


		vma = radix_tree_delete(&ctx->handles_vma, lut->handle);



		if (!i915_vma_is_ggtt(vma))

		GEM_BUG_ON(vma->obj != obj);



		/* We allow the process to have multiple handles to the same

		 * vma, in the same fd namespace, by virtue of flink/open.

		 */

		GEM_BUG_ON(!vma->open_count);

		if (!--vma->open_count && !i915_vma_is_ggtt(vma))

			i915_vma_close(vma);



		list_del(&lut->obj_link);