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Commit 7d859ff4 authored by Kyoungil Kim's avatar Kyoungil Kim Committed by Grant Likely
Browse files

spi: Change FIFO flush operation and spi channel off 



Setting SW_RST does TX/RX FIFO flush.
After FIFO flush, SW_RST should be cleared.
The above setting and clearing SW_RST operation should be done after spi channel off.

Signed-off-by: default avatarKyoungil Kim <ki0351.kim@samsung.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
parent 6f38010d

drivers/spi/spi-s3c64xx.c

+4 −4
Original line number Diff line number Diff line
@@ -214,6 +214,10 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 


	writel(0, regs + S3C64XX_SPI_PACKET_CNT);



	val = readl(regs + S3C64XX_SPI_CH_CFG);

	val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);

	writel(val, regs + S3C64XX_SPI_CH_CFG);



	val = readl(regs + S3C64XX_SPI_CH_CFG);

	val |= S3C64XX_SPI_CH_SW_RST;

	val &= ~S3C64XX_SPI_CH_HS_EN;
@@ -248,10 +252,6 @@ static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 
	val = readl(regs + S3C64XX_SPI_MODE_CFG);

	val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);

	writel(val, regs + S3C64XX_SPI_MODE_CFG);



	val = readl(regs + S3C64XX_SPI_CH_CFG);

	val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);

	writel(val, regs + S3C64XX_SPI_CH_CFG);

}



static void s3c64xx_spi_dmacb(void *data)