Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7d708ee4 authored by Imre Deak's avatar Imre Deak Committed by Daniel Vetter
Browse files

drm/i915: HSW: allow PCH clock gating for suspend 



For the device to enter D3 we should enable PCH clock gating.

v2:
- use HAS_PCH_LPT instead of IS_HASWELL (Ville, Paolo)
- rename lpt_allow_clock_gating to lpt_suspend_hw (Paolo)

Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bc5ead8c

drivers/gpu/drm/i915/i915_drv.c

+2 −0
Original line number Diff line number Diff line
@@ -529,6 +529,8 @@ static int i915_drm_freeze(struct drm_device *dev) 
		 */

		list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

			dev_priv->display.crtc_disable(crtc);



		intel_modeset_suspend_hw(dev);

	}



	i915_save_state(dev);

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1865,6 +1865,7 @@ static inline void intel_unregister_dsm_handler(void) { return; } 


/* modesetting */

extern void intel_modeset_init_hw(struct drm_device *dev);

extern void intel_modeset_suspend_hw(struct drm_device *dev);

extern void intel_modeset_init(struct drm_device *dev);

extern void intel_modeset_gem_init(struct drm_device *dev);

extern void intel_modeset_cleanup(struct drm_device *dev);

drivers/gpu/drm/i915/intel_display.c

+5 −0
Original line number Diff line number Diff line
@@ -9271,6 +9271,11 @@ void intel_modeset_init_hw(struct drm_device *dev) 
	mutex_unlock(&dev->struct_mutex);

}



void intel_modeset_suspend_hw(struct drm_device *dev)

{

	intel_suspend_hw(dev);

}



void intel_modeset_init(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

drivers/gpu/drm/i915/intel_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -716,6 +716,7 @@ extern void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, 
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)



extern void intel_init_clock_gating(struct drm_device *dev);

extern void intel_suspend_hw(struct drm_device *dev);

extern void intel_write_eld(struct drm_encoder *encoder,

			    struct drm_display_mode *mode);

extern void intel_prepare_ddi(struct drm_device *dev);

drivers/gpu/drm/i915/intel_pm.c

+18 −0
Original line number Diff line number Diff line
@@ -3988,6 +3988,18 @@ static void lpt_init_clock_gating(struct drm_device *dev) 
			   PCH_LP_PARTITION_LEVEL_DISABLE);

}



static void lpt_suspend_hw(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;



	if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {

		uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);



		val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;

		I915_WRITE(SOUTH_DSPCLK_GATE_D, val);

	}

}



static void haswell_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4340,6 +4352,12 @@ void intel_init_clock_gating(struct drm_device *dev) 
	dev_priv->display.init_clock_gating(dev);

}



void intel_suspend_hw(struct drm_device *dev)

{

	if (HAS_PCH_LPT(dev))

		lpt_suspend_hw(dev);

}



/**

 * We should only use the power well if we explicitly asked the hardware to

 * enable it, so check if it's enabled and also check if we've requested it to