Loading arch/arc/Kconfig +1 −5 Original line number Diff line number Diff line Loading @@ -136,9 +136,6 @@ if SMP config ARC_HAS_COH_CACHES def_bool n config ARC_HAS_COH_RTSC def_bool n config ARC_HAS_REENTRANT_IRQ_LV2 def_bool n Loading Loading @@ -332,8 +329,7 @@ config ARC_HAS_RTSC bool "Insn: RTSC (64-bit r/o cycle counter)" default y depends on ARC_CPU_REL_4_10 # if SMP, enable RTSC only if counter is coherent across cores depends on !SMP || ARC_HAS_COH_RTSC depends on !SMP endmenu # "ARC CPU Configuration" Loading arch/arc/kernel/time.c +4 −3 Original line number Diff line number Diff line Loading @@ -63,9 +63,10 @@ int arc_counter_setup(void) { /* RTSC insn taps into cpu clk, needs no setup */ /* For SMP, only allowed if cross-core-sync, hence usable as cs */ /* * For SMP this needs to be 0. However Kconfig glue doesn't * enable this option for SMP configs */ return 1; } Loading Loading
arch/arc/Kconfig +1 −5 Original line number Diff line number Diff line Loading @@ -136,9 +136,6 @@ if SMP config ARC_HAS_COH_CACHES def_bool n config ARC_HAS_COH_RTSC def_bool n config ARC_HAS_REENTRANT_IRQ_LV2 def_bool n Loading Loading @@ -332,8 +329,7 @@ config ARC_HAS_RTSC bool "Insn: RTSC (64-bit r/o cycle counter)" default y depends on ARC_CPU_REL_4_10 # if SMP, enable RTSC only if counter is coherent across cores depends on !SMP || ARC_HAS_COH_RTSC depends on !SMP endmenu # "ARC CPU Configuration" Loading
arch/arc/kernel/time.c +4 −3 Original line number Diff line number Diff line Loading @@ -63,9 +63,10 @@ int arc_counter_setup(void) { /* RTSC insn taps into cpu clk, needs no setup */ /* For SMP, only allowed if cross-core-sync, hence usable as cs */ /* * For SMP this needs to be 0. However Kconfig glue doesn't * enable this option for SMP configs */ return 1; } Loading