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Commit 7cd88edc authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Greg Kroah-Hartman
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mtd: spi-nor: cadence-quadspi: Make driver independent of flash geometry 



[ Upstream commit 834b4e8d344139ba64cda22099b2b2ef6c9a542d ]

Drop configuration of Flash size, erase size and page size
configuration. Flash size is needed only if using AHB decoder (BIT 23 of
CONFIG_REG) which is not used by the driver.
Erase size and page size are needed if IP is configured to send WREN
automatically. But since SPI NOR layer takes care of sending WREN, there
is no need to configure these fields either.

Therefore drop these in preparation to move the driver to spi-mem
framework where flash geometry is not visible to controller driver.

Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Acked-by: default avatarTudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20200601070444.16923-2-vigneshr@ti.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Stable-dep-of: 2087e85bb66e ("spi: cadence-quadspi: fix suspend-resume implementations")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent e5f7e4b2

drivers/mtd/spi-nor/cadence-quadspi.c

+1 −35
Original line number Diff line number Diff line
@@ -80,9 +80,6 @@ struct cqspi_st { 
	dma_addr_t		mmap_phys_base;



	int			current_cs;

	int			current_page_size;

	int			current_erase_size;

	int			current_addr_width;

	unsigned long		master_ref_clk_hz;

	bool			is_decoded_cs;

	u32			fifo_depth;
@@ -734,32 +731,6 @@ static void cqspi_chipselect(struct spi_nor *nor) 
	writel(reg, reg_base + CQSPI_REG_CONFIG);

}



static void cqspi_configure_cs_and_sizes(struct spi_nor *nor)

{

	struct cqspi_flash_pdata *f_pdata = nor->priv;

	struct cqspi_st *cqspi = f_pdata->cqspi;

	void __iomem *iobase = cqspi->iobase;

	unsigned int reg;



	/* configure page size and block size. */

	reg = readl(iobase + CQSPI_REG_SIZE);

	reg &= ~(CQSPI_REG_SIZE_PAGE_MASK << CQSPI_REG_SIZE_PAGE_LSB);

	reg &= ~(CQSPI_REG_SIZE_BLOCK_MASK << CQSPI_REG_SIZE_BLOCK_LSB);

	reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;

	reg |= (nor->page_size << CQSPI_REG_SIZE_PAGE_LSB);

	reg |= (ilog2(nor->mtd.erasesize) << CQSPI_REG_SIZE_BLOCK_LSB);

	reg |= (nor->addr_width - 1);

	writel(reg, iobase + CQSPI_REG_SIZE);



	/* configure the chip select */

	cqspi_chipselect(nor);



	/* Store the new configuration of the controller */

	cqspi->current_page_size = nor->page_size;

	cqspi->current_erase_size = nor->mtd.erasesize;

	cqspi->current_addr_width = nor->addr_width;

}



static unsigned int calculate_ticks_for_ns(const unsigned int ref_clk_hz,

					   const unsigned int ns_val)

{
@@ -865,18 +836,13 @@ static void cqspi_configure(struct spi_nor *nor) 
	int switch_cs = (cqspi->current_cs != f_pdata->cs);

	int switch_ck = (cqspi->sclk != sclk);



	if ((cqspi->current_page_size != nor->page_size) ||

	    (cqspi->current_erase_size != nor->mtd.erasesize) ||

	    (cqspi->current_addr_width != nor->addr_width))

		switch_cs = 1;



	if (switch_cs || switch_ck)

		cqspi_controller_enable(cqspi, 0);



	/* Switch chip select. */

	if (switch_cs) {

		cqspi->current_cs = f_pdata->cs;

		cqspi_configure_cs_and_sizes(nor);

		cqspi_chipselect(nor);

	}



	/* Setup baudrate divisor and delays */