Merge tag 'kvm-3.15-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm

4.24 KVM_CREATE_IRQCHIP

Capability: KVM_CAP_IRQCHIP

Architectures: x86, ia64, ARM, arm64

Capability: KVM_CAP_IRQCHIP, KVM_CAP_S390_IRQCHIP (s390)

Architectures: x86, ia64, ARM, arm64, s390

Type: vm ioctl

Parameters: none

Returns: 0 on success, -1 on error

ioapic, a virtual PIC (two PICs, nested), and sets up future vcpus to have a

local APIC.  IRQ routing for GSIs 0-15 is set to both PIC and IOAPIC; GSI 16-23

only go to the IOAPIC.  On ia64, a IOSAPIC is created. On ARM/arm64, a GIC is

created.

created. On s390, a dummy irq routing table is created.

Note that on s390 the KVM_CAP_S390_IRQCHIP vm capability needs to be enabled

before KVM_CREATE_IRQCHIP can be used.

4.25 KVM_IRQ_LINE

been previously created with KVM_CREATE_IRQCHIP.  Note that edge-triggered

interrupts require the level to be set to 1 and then back to 0.

On real hardware, interrupt pins can be active-low or active-high.  This

does not matter for the level field of struct kvm_irq_level: 1 always

means active (asserted), 0 means inactive (deasserted).

x86 allows the operating system to program the interrupt polarity

(active-low/active-high) for level-triggered interrupts, and KVM used

to consider the polarity.  However, due to bitrot in the handling of

active-low interrupts, the above convention is now valid on x86 too.

This is signaled by KVM_CAP_X86_IOAPIC_POLARITY_IGNORED.  Userspace

should not present interrupts to the guest as active-low unless this

capability is present (or unless it is not using the in-kernel irqchip,

of course).

ARM/arm64 can signal an interrupt either at the CPU level, or at the

in-kernel irqchip (GIC), and for in-kernel irqchip can tell the GIC to

use PPIs designated for specific cpus.  The irq field is interpreted

(The irq_id field thus corresponds nicely to the IRQ ID in the ARM GIC specs)

In both cases, level is used to raise/lower the line.

In both cases, level is used to assert/deassert the line.

struct kvm_irq_level {

	union {

4.37 KVM_ENABLE_CAP

Capability: KVM_CAP_ENABLE_CAP

Capability: KVM_CAP_ENABLE_CAP, KVM_CAP_ENABLE_CAP_VM

Architectures: ppc, s390

Type: vcpu ioctl

Type: vcpu ioctl, vm ioctl (with KVM_CAP_ENABLE_CAP_VM)

Parameters: struct kvm_enable_cap (in)

Returns: 0 on success; -1 on error

       __u8  pad[64];

};

The vcpu ioctl should be used for vcpu-specific capabilities, the vm ioctl

for vm-wide capabilities.

4.38 KVM_GET_MP_STATE

4.52 KVM_SET_GSI_ROUTING

Capability: KVM_CAP_IRQ_ROUTING

Architectures: x86 ia64

Architectures: x86 ia64 s390

Type: vm ioctl

Parameters: struct kvm_irq_routing (in)

Returns: 0 on success, -1 on error

	union {

		struct kvm_irq_routing_irqchip irqchip;

		struct kvm_irq_routing_msi msi;

		struct kvm_irq_routing_s390_adapter adapter;

		__u32 pad[8];

	} u;

};

/* gsi routing entry types */

#define KVM_IRQ_ROUTING_IRQCHIP 1

#define KVM_IRQ_ROUTING_MSI 2

#define KVM_IRQ_ROUTING_S390_ADAPTER 3

No flags are specified so far, the corresponding field must be set to zero.

	__u32 pad;

};

struct kvm_irq_routing_s390_adapter {

	__u64 ind_addr;

	__u64 summary_addr;

	__u64 ind_offset;

	__u32 summary_offset;

	__u32 adapter_id;

};

4.53 KVM_ASSIGN_SET_MSIX_NR

by kvm.  The 'data' member contains the written data if 'is_write' is

true, and should be filled by application code otherwise.

The 'data' member contains, in its first 'len' bytes, the value as it would

appear if the VCPU performed a load or store of the appropriate width directly

to the byte array.

NOTE: For KVM_EXIT_IO, KVM_EXIT_MMIO, KVM_EXIT_OSI, KVM_EXIT_DCR,

      KVM_EXIT_PAPR and KVM_EXIT_EPR the corresponding

operations are complete (and guest state is consistent) only after userspace

FLIC (floating interrupt controller)

====================================

FLIC handles floating (non per-cpu) interrupts, i.e. I/O, service and some

machine check interruptions. All interrupts are stored in a per-vm list of

pending interrupts. FLIC performs operations on this list.

Only one FLIC instance may be instantiated.

FLIC provides support to

- add interrupts (KVM_DEV_FLIC_ENQUEUE)

- inspect currently pending interrupts (KVM_FLIC_GET_ALL_IRQS)

- purge all pending floating interrupts (KVM_DEV_FLIC_CLEAR_IRQS)

- enable/disable for the guest transparent async page faults

- register and modify adapter interrupt sources (KVM_DEV_FLIC_ADAPTER_*)

Groups:

  KVM_DEV_FLIC_ENQUEUE

    Passes a buffer and length into the kernel which are then injected into

    the list of pending interrupts.

    attr->addr contains the pointer to the buffer and attr->attr contains

    the length of the buffer.

    The format of the data structure kvm_s390_irq as it is copied from userspace

    is defined in usr/include/linux/kvm.h.

  KVM_DEV_FLIC_GET_ALL_IRQS

    Copies all floating interrupts into a buffer provided by userspace.

    When the buffer is too small it returns -ENOMEM, which is the indication

    for userspace to try again with a bigger buffer.

    All interrupts remain pending, i.e. are not deleted from the list of

    currently pending interrupts.

    attr->addr contains the userspace address of the buffer into which all

    interrupt data will be copied.

    attr->attr contains the size of the buffer in bytes.

  KVM_DEV_FLIC_CLEAR_IRQS

    Simply deletes all elements from the list of currently pending floating

    interrupts.  No interrupts are injected into the guest.

  KVM_DEV_FLIC_APF_ENABLE

    Enables async page faults for the guest. So in case of a major page fault

    the host is allowed to handle this async and continues the guest.

  KVM_DEV_FLIC_APF_DISABLE_WAIT

    Disables async page faults for the guest and waits until already pending

    async page faults are done. This is necessary to trigger a completion interrupt

    for every init interrupt before migrating the interrupt list.

  KVM_DEV_FLIC_ADAPTER_REGISTER

    Register an I/O adapter interrupt source. Takes a kvm_s390_io_adapter

    describing the adapter to register:

struct kvm_s390_io_adapter {

	__u32 id;

	__u8 isc;

	__u8 maskable;

	__u8 swap;

	__u8 pad;

};

   id contains the unique id for the adapter, isc the I/O interruption subclass

   to use, maskable whether this adapter may be masked (interrupts turned off)

   and swap whether the indicators need to be byte swapped.

  KVM_DEV_FLIC_ADAPTER_MODIFY

    Modifies attributes of an existing I/O adapter interrupt source. Takes

    a kvm_s390_io_adapter_req specifiying the adapter and the operation:

struct kvm_s390_io_adapter_req {

	__u32 id;

	__u8 type;

	__u8 mask;

	__u16 pad0;

	__u64 addr;

};

    id specifies the adapter and type the operation. The supported operations

    are:

    KVM_S390_IO_ADAPTER_MASK

      mask or unmask the adapter, as specified in mask

    KVM_S390_IO_ADAPTER_MAP

      perform a gmap translation for the guest address provided in addr,

      pin a userspace page for the translated address and add it to the

      list of mappings

    KVM_S390_IO_ADAPTER_UNMAP

      release a userspace page for the translated address specified in addr

      from the list of mappings

 * The bits we set in HCR:

 * TAC:		Trap ACTLR

 * TSC:		Trap SMC

 * TVM:		Trap VM ops (until MMU and caches are on)

 * TSW:		Trap cache operations by set/way

 * TWI:		Trap WFI

 * TWE:		Trap WFE

 */

#define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \

			HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \

			HCR_TWE | HCR_SWIO | HCR_TIDCP)

#define HCR_VIRT_EXCP_MASK (HCR_VA | HCR_VI | HCR_VF)

			HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP)

/* System Control Register (SCTLR) bits */

#define SCTLR_TE	(1 << 30)

#define c13_TID_URO	26	/* Thread ID, User R/O */

#define c13_TID_PRIV	27	/* Thread ID, Privileged */

#define c14_CNTKCTL	28	/* Timer Control Register (PL1) */

#define NR_CP15_REGS	29	/* Number of regs (incl. invalid) */

#define c10_AMAIR0	29	/* Auxilary Memory Attribute Indirection Reg0 */

#define c10_AMAIR1	30	/* Auxilary Memory Attribute Indirection Reg1 */

#define NR_CP15_REGS	31	/* Number of regs (incl. invalid) */

#define ARM_EXCEPTION_RESET	  0

#define ARM_EXCEPTION_UNDEFINED   1

	/* The CPU type we expose to the VM */

	u32 midr;

	/* HYP trapping configuration */

	u32 hcr;

	/* Interrupt related fields */

	u32 irq_lines;		/* IRQ and FIQ levels */

	/* Exception Information */

	struct kvm_vcpu_fault_info fault;

	/* IO related fields */

	struct kvm_decode mmio_decode;

	/* Interrupt related fields */

	u32 irq_lines;		/* IRQ and FIQ levels */

	/* Cache some mmu pages needed inside spinlock regions */

	struct kvm_mmu_memory_cache mmu_page_cache;