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Commit 7c863844 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: khaje: Update clock changes for GCC/GPUCC/DISPCC"

parents ca2861a8 c6fefb6d

drivers/clk/qcom/dispcc-khaje.c

+1 −1
Original line number Diff line number Diff line
@@ -110,7 +110,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { 
			.name = "disp_cc_pll0",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_lucid_ops,

			.vdd_class = &vdd_cx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {

drivers/clk/qcom/gcc-khaje.c

+2 −2
Original line number Diff line number Diff line
@@ -3100,7 +3100,7 @@ static struct clk_branch gcc_ufs_phy_axi_clk = { 


static struct clk_branch gcc_ufs_phy_ice_core_clk = {

	.halt_reg = 0x45044,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_VOTED,

	.hwcg_reg = 0x45044,

	.hwcg_bit = 1,

	.clkr = {
@@ -3153,7 +3153,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { 


static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {

	.halt_reg = 0x4509c,

	.halt_check = BRANCH_HALT,

	.halt_check = BRANCH_HALT_SKIP,

	.clkr = {

		.enable_reg = 0x4509c,

		.enable_mask = BIT(0),

drivers/clk/qcom/gpucc-khaje.c

+4 −5
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 
static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);

static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);





enum {

	P_BI_TCXO,

	P_GPLL0_OUT_MAIN,
@@ -51,8 +50,8 @@ static const char * const gpu_cc_parent_names_0[] = { 
	"bi_tcxo",

	"gpu_cc_pll0_out_main",

	"gpu_cc_pll1",

	"gpll0_out_main",

	"gpll0_out_main_div",

	"gcc_gpu_gpll0_clk_src",

	"gcc_gpu_gpll0_div_clk_src",

};



static const struct parent_map gpu_cc_parent_map_1[] = {
@@ -70,7 +69,7 @@ static const char * const gpu_cc_parent_names_1[] = { 
	"gpu_cc_pll0",

	"gpu_cc_pll1",

	"gpu_cc_pll1",

	"gpll0_out_main",

	"gcc_gpu_gpll0_clk_src",

};



static struct pll_vco lucid_vco[] = {
@@ -158,7 +157,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { 
			.name = "gpu_cc_pll1",

			.parent_names = (const char *[]){ "bi_tcxo" },

			.num_parents = 1,

			.ops = &clk_alpha_pll_ops,

			.ops = &clk_alpha_pll_lucid_ops,

			.vdd_class = &vdd_mx,

			.num_rate_max = VDD_NUM,

			.rate_max = (unsigned long[VDD_NUM]) {