Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7c607944 authored by Mylène Josserand's avatar Mylène Josserand Committed by Maxime Ripard
Browse files

ARM: smp: Add initialization of CNTVOFF 



The CNTVOFF register from arch timer is uninitialized.
It should be done by the bootloader but it is currently not the case,
even for boot CPU because this SoC is booting in secure mode.
It leads to an random offset value meaning that each CPU will have a
different time, which isn't working very well.

Add assembly code used for boot CPU and secondary CPU cores to make
sure that the CNTVOFF register is initialized. Because this code can
be used by different platforms, add this assembly file in ARM's common
folder.

Signed-off-by: default avatarMylène Josserand <mylene.josserand@bootlin.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Tested-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent dff052cc

arch/arm/common/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o 
obj-$(CONFIG_SHARP_LOCOMO)	+= locomo.o

obj-$(CONFIG_SHARP_PARAM)	+= sharpsl_param.o

obj-$(CONFIG_SHARP_SCOOP)	+= scoop.o

obj-$(CONFIG_SMP)		+= secure_cntvoff.o

obj-$(CONFIG_PCI_HOST_ITE8152)  += it8152.o

obj-$(CONFIG_MCPM)		+= mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o

CFLAGS_REMOVE_mcpm_entry.o	= -pg

arch/arm/common/secure_cntvoff.S

0 → 100644
+32 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2014 Renesas Electronics Corporation

 *

 * Initialization of CNTVOFF register from secure mode

 *

 */



#include <linux/linkage.h>

#include <asm/assembler.h>



ENTRY(secure_cntvoff_init)

	.arch	armv7-a

	/*

	 * CNTVOFF has to be initialized either from non-secure Hypervisor

	 * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled

	 * then it should be handled by the secure code. The CPU must implement

	 * the virtualization extensions.

	 */

	cps	#MON_MODE

	mrc	p15, 0, r1, c1, c1, 0		/* Get Secure Config */

	orr	r0, r1, #1

	mcr	p15, 0, r0, c1, c1, 0		/* Set Non Secure bit */

	isb

	mov	r0, #0

	mcrr	p15, 4, r0, r0, c14		/* CNTVOFF = 0 */

	isb

	mcr	p15, 0, r1, c1, c1, 0		/* Set Secure bit */

	isb

	cps	#SVC_MODE

	ret	lr

ENDPROC(secure_cntvoff_init)

arch/arm/include/asm/secure_cntvoff.h

0 → 100644
+8 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */



#ifndef __ASMARM_ARCH_CNTVOFF_H

#define __ASMARM_ARCH_CNTVOFF_H



extern void secure_cntvoff_init(void);



#endif