Loading drivers/clk/qcom/gcc-kona.c +2 −2 Original line number Diff line number Diff line Loading @@ -432,11 +432,11 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_refgen_clk_src", .parent_names = gcc_parent_names_0, .parent_names = gcc_parent_names_0_ao, .num_parents = 4, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .vdd_class = &vdd_cx_ao, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 19200000, Loading Loading
drivers/clk/qcom/gcc-kona.c +2 −2 Original line number Diff line number Diff line Loading @@ -432,11 +432,11 @@ static struct clk_rcg2 gcc_pcie_phy_refgen_clk_src = { .freq_tbl = ftbl_gcc_pcie_phy_refgen_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_pcie_phy_refgen_clk_src", .parent_names = gcc_parent_names_0, .parent_names = gcc_parent_names_0_ao, .num_parents = 4, .flags = CLK_SET_RATE_PARENT, .ops = &clk_rcg2_ops, .vdd_class = &vdd_cx, .vdd_class = &vdd_cx_ao, .num_rate_max = VDD_NUM, .rate_max = (unsigned long[VDD_NUM]) { [VDD_MIN] = 19200000, Loading