Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7a70d728 authored by Paul Mackerras's avatar Paul Mackerras Committed by Michael Ellerman
Browse files

powerpc/64: Invalidate process table caching after setting process table 



The POWER9 MMU reads and caches entries from the process table.
When we kexec from one kernel to another, the second kernel sets
its process table pointer but doesn't currently do anything to
make the CPU invalidate any cached entries from the old process table.
This adds a tlbie (TLB invalidate entry) instruction with parameters
to invalidate caching of the process table after the new process
table is installed.

Signed-off-by: default avatarPaul Mackerras <paulus@ozlabs.org>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 4ceae137

arch/powerpc/mm/pgtable-radix.c

+4 −0
Original line number Diff line number Diff line
@@ -186,6 +186,10 @@ static void __init radix_init_pgtable(void) 
	 */

	register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);

	pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);

	asm volatile("ptesync" : : : "memory");

	asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :

		     "r" (TLBIEL_INVAL_SET_LPID), "r" (0));

	asm volatile("eieio; tlbsync; ptesync" : : : "memory");

}



static void __init radix_init_partition_table(void)