Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7a52b6de authored by Laurent Pinchart's avatar Laurent Pinchart Committed by Mauro Carvalho Chehab
Browse files

[media] v4l: vsp1: Add alpha channel support to the memory ports 



Support ARGB formats on the RPF side by reading the alpha component from
memory and on the WPF side by writing it to memory.

Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: default avatarMauro Carvalho Chehab <m.chehab@samsung.com>
parent 56bfef3e

drivers/media/platform/vsp1/vsp1_rpf.c

+5 −3
Original line number Original line Diff line number Diff line
@@ -101,10 +101,12 @@ static int rpf_s_stream(struct v4l2_subdev *subdev, int enable) 
		       (rpf->location.left << VI6_RPF_LOC_HCOORD_SHIFT) |

		       (rpf->location.left << VI6_RPF_LOC_HCOORD_SHIFT) |

		       (rpf->location.top << VI6_RPF_LOC_VCOORD_SHIFT));

		       (rpf->location.top << VI6_RPF_LOC_VCOORD_SHIFT));





	/* Disable alpha, mask and color key. Set the alpha channel to a fixed

	/* Use the alpha channel (extended to 8 bits) when available or a

	 * value of 255.

	 * hardcoded 255 value otherwise. Disable color keying.

	 */

	 */

	vsp1_rpf_write(rpf, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_ASEL_FIXED);

	vsp1_rpf_write(rpf, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT |

		       (fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED

				       : VI6_RPF_ALPH_SEL_ASEL_FIXED));

	vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET,

	vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET,

		       255 << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);

		       255 << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);

	vsp1_rpf_write(rpf, VI6_RPF_MSK_CTRL, 0);

	vsp1_rpf_write(rpf, VI6_RPF_MSK_CTRL, 0);

drivers/media/platform/vsp1/vsp1_video.c

+32 −17
Original line number Original line Diff line number Diff line
@@ -50,70 +50,85 @@ static const struct vsp1_format_info vsp1_video_formats[] = { 
	{ V4L2_PIX_FMT_RGB332, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_RGB332, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 8, 0, 0 }, false, false, 1, 1 },

	  1, { 8, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_ARGB444, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS,

	  1, { 16, 0, 0 }, false, false, 1, 1, true },

	{ V4L2_PIX_FMT_XRGB444, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_XRGB444, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS,

	  VI6_RPF_DSWAP_P_WDS,

	  1, { 16, 0, 0 }, false, false, 1, 1 },

	  1, { 16, 0, 0 }, false, false, 1, 1, true },

	{ V4L2_PIX_FMT_ARGB555, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS,

	  1, { 16, 0, 0 }, false, false, 1, 1, true },

	{ V4L2_PIX_FMT_XRGB555, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_XRGB555, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS,

	  VI6_RPF_DSWAP_P_WDS,

	  1, { 16, 0, 0 }, false, false, 1, 1 },

	  1, { 16, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_RGB565, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_RGB565, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS,

	  VI6_RPF_DSWAP_P_WDS,

	  1, { 16, 0, 0 }, false, false, 1, 1 },

	  1, { 16, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_BGR24, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_BGR24, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 24, 0, 0 }, false, false, 1, 1 },

	  1, { 24, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_RGB24, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_RGB24, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 24, 0, 0 }, false, false, 1, 1 },

	  1, { 24, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_ABGR32, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,

	  1, { 32, 0, 0 }, false, false, 1, 1, true },

	{ V4L2_PIX_FMT_XBGR32, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_XBGR32, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,

	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,

	  1, { 32, 0, 0 }, false, false, 1, 1 },

	  1, { 32, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_ARGB32, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 32, 0, 0 }, false, false, 1, 1, true },

	{ V4L2_PIX_FMT_XRGB32, V4L2_MBUS_FMT_ARGB8888_1X32,

	{ V4L2_PIX_FMT_XRGB32, V4L2_MBUS_FMT_ARGB8888_1X32,

	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 32, 0, 0 }, false, false, 1, 1 },

	  1, { 32, 0, 0 }, false, false, 1, 1, false },

	{ V4L2_PIX_FMT_UYVY, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_UYVY, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 16, 0, 0 }, false, false, 2, 1 },

	  1, { 16, 0, 0 }, false, false, 2, 1, false },

	{ V4L2_PIX_FMT_VYUY, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_VYUY, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 16, 0, 0 }, false, true, 2, 1 },

	  1, { 16, 0, 0 }, false, true, 2, 1, false },

	{ V4L2_PIX_FMT_YUYV, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_YUYV, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 16, 0, 0 }, true, false, 2, 1 },

	  1, { 16, 0, 0 }, true, false, 2, 1, false },

	{ V4L2_PIX_FMT_YVYU, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_YVYU, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  1, { 16, 0, 0 }, true, true, 2, 1 },

	  1, { 16, 0, 0 }, true, true, 2, 1, false },

	{ V4L2_PIX_FMT_NV12M, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_NV12M, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  2, { 8, 16, 0 }, false, false, 2, 2 },

	  2, { 8, 16, 0 }, false, false, 2, 2, false },

	{ V4L2_PIX_FMT_NV21M, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_NV21M, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  2, { 8, 16, 0 }, false, true, 2, 2 },

	  2, { 8, 16, 0 }, false, true, 2, 2, false },

	{ V4L2_PIX_FMT_NV16M, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_NV16M, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  2, { 8, 16, 0 }, false, false, 2, 1 },

	  2, { 8, 16, 0 }, false, false, 2, 1, false },

	{ V4L2_PIX_FMT_NV61M, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_NV61M, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  2, { 8, 16, 0 }, false, true, 2, 1 },

	  2, { 8, 16, 0 }, false, true, 2, 1, false },

	{ V4L2_PIX_FMT_YUV420M, V4L2_MBUS_FMT_AYUV8_1X32,

	{ V4L2_PIX_FMT_YUV420M, V4L2_MBUS_FMT_AYUV8_1X32,

	  VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,

	  3, { 8, 8, 8 }, false, false, 2, 2 },

	  3, { 8, 8, 8 }, false, false, 2, 2, false },

};

};





/*

/*

drivers/media/platform/vsp1/vsp1_video.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -33,6 +33,7 @@ struct vsp1_video; 
 * @swap_uv: the U and V components are swapped (V comes before U)

 * @swap_uv: the U and V components are swapped (V comes before U)

 * @hsub: horizontal subsampling factor

 * @hsub: horizontal subsampling factor

 * @vsub: vertical subsampling factor

 * @vsub: vertical subsampling factor

 * @alpha: has an alpha channel

 */

 */

struct vsp1_format_info {

struct vsp1_format_info {

	u32 fourcc;

	u32 fourcc;
@@ -45,6 +46,7 @@ struct vsp1_format_info { 
	bool swap_uv;

	bool swap_uv;

	unsigned int hsub;

	unsigned int hsub;

	unsigned int vsub;

	unsigned int vsub;

	bool alpha;

};

};





enum vsp1_pipeline_state {

enum vsp1_pipeline_state {

drivers/media/platform/vsp1/vsp1_wpf.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -99,6 +99,8 @@ static int wpf_s_stream(struct v4l2_subdev *subdev, int enable) 




		outfmt = fmtinfo->hwfmt << VI6_WPF_OUTFMT_WRFMT_SHIFT;

		outfmt = fmtinfo->hwfmt << VI6_WPF_OUTFMT_WRFMT_SHIFT;





		if (fmtinfo->alpha)

			outfmt |= VI6_WPF_OUTFMT_PXA;

		if (fmtinfo->swap_yc)

		if (fmtinfo->swap_yc)

			outfmt |= VI6_WPF_OUTFMT_SPYCS;

			outfmt |= VI6_WPF_OUTFMT_SPYCS;

		if (fmtinfo->swap_uv)

		if (fmtinfo->swap_uv)