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Unverified Commit 7a3b1bf7 authored by Palmer Dabbelt's avatar Palmer Dabbelt
Browse files

RISC-V: Fix sys_riscv_flush_icache 

This contains a pair of patches that together fix sys_riscv_flush_icache
on all systems:

* The first enables sys_riscv_flush_icache() for non-SMP systems.
* The second fixes a bug in our syscall header that caused
  sys_riscv_flush_icache to never get generated.
parents 66eb957d e45c7aca

arch/riscv/include/asm/unistd.h

+5 −0
Original line number Diff line number Diff line
@@ -11,6 +11,11 @@ 
 *   GNU General Public License for more details.

 */



/*

 * There is explicitly no include guard here because this file is expected to

 * be included multiple times.  See uapi/asm/syscalls.h for more info.

 */



#define __ARCH_WANT_SYS_CLONE

#include <uapi/asm/unistd.h>

#include <uapi/asm/syscalls.h>

arch/riscv/include/asm/vdso.h

+0 −2
Original line number Diff line number Diff line
@@ -38,8 +38,6 @@ struct vdso_data { 
	(void __user *)((unsigned long)(base) + __vdso_##name);			\

})



#ifdef CONFIG_SMP

asmlinkage long sys_riscv_flush_icache(uintptr_t, uintptr_t, uintptr_t);

#endif



#endif /* _ASM_RISCV_VDSO_H */

arch/riscv/include/uapi/asm/syscalls.h

+8 −5
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */

/*

 * Copyright (C) 2017 SiFive

 * Copyright (C) 2017-2018 SiFive

 */



#ifndef _ASM__UAPI__SYSCALLS_H

#define _ASM__UAPI__SYSCALLS_H

/*

 * There is explicitly no include guard here because this file is expected to

 * be included multiple times in order to define the syscall macros via

 * __SYSCALL.

 */



/*

 * Allows the instruction cache to be flushed from userspace.  Despite RISC-V
@@ -20,7 +23,7 @@ 
 * caller.  We don't currently do anything with the address range, that's just

 * in there for forwards compatibility.

 */

#ifndef __NR_riscv_flush_icache

#define __NR_riscv_flush_icache (__NR_arch_specific_syscall + 15)

__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)



#endif

__SYSCALL(__NR_riscv_flush_icache, sys_riscv_flush_icache)

arch/riscv/kernel/sys_riscv.c

+10 −2
Original line number Diff line number Diff line
@@ -48,7 +48,6 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 
}

#endif /* !CONFIG_64BIT */



#ifdef CONFIG_SMP

/*

 * Allows the instruction cache to be flushed from userspace.  Despite RISC-V

 * having a direct 'fence.i' instruction available to userspace (which we
@@ -66,15 +65,24 @@ SYSCALL_DEFINE6(mmap2, unsigned long, addr, unsigned long, len, 
SYSCALL_DEFINE3(riscv_flush_icache, uintptr_t, start, uintptr_t, end,

	uintptr_t, flags)

{

#ifdef CONFIG_SMP

	struct mm_struct *mm = current->mm;

	bool local = (flags & SYS_RISCV_FLUSH_ICACHE_LOCAL) != 0;

#endif



	/* Check the reserved flags. */

	if (unlikely(flags & ~SYS_RISCV_FLUSH_ICACHE_ALL))

		return -EINVAL;



	/*

	 * Without CONFIG_SMP flush_icache_mm is a just a flush_icache_all(),

	 * which generates unused variable warnings all over this function.

	 */

#ifdef CONFIG_SMP

	flush_icache_mm(mm, local);

#else

	flush_icache_all();

#endif



	return 0;

}
 
#endif