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Commit 79b3c716 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux into drm-next 

AMD GPU bugfixes:
- Various powerplay bug fixes
- Add some new polaris pci ids
- misc bug fixes and code cleanups

* 'drm-next-4.7' of git://people.freedesktop.org/~agd5f/linux: (27 commits)
  drm/amd: add Kconfig dependency for ACP on DRM_AMDGPU
  drm/amdgpu: Fix hdmi deep color support.
  drm/amdgpu: fix bug in fence driver fini
  drm/amd/powerplay/hwmgr: use kmemdup
  drm/amd/powerplay/hwmgr: use kmemdup
  drm/amd/powerplay/hwmgr: use kmemdup
  drm/amd/powerplay: fix bugs of checking if dpm is running on Tonga
  drm/amdgpu: update Polaris11 golden setting
  drm/amdgpu: Add more Polaris 11 PCI IDs
  drm/amdgpu: update Polaris10 golden setting
  drm/amdgpu: add more Polaris10 DID
  drm/amd/amdgpu : Remove unused variable
  drm/amd/amdgpu : Remove unused variable
  drm/amd/amdgpu : Remove unused variable
  drm/amd/amdgpu/cz_dpm: Remove unused variable
  drm/amd/amdgpu : Remove unused variable
  drm/amd/powerplay: use ARRAY_SIZE() to calculate array size.
  drm/amdgpu: fix array out of bounds
  drm/radeon: fix array out of bounds
  drm/amd/powerplay: fix a bug on updating sclk for Tonga
  ...
parents e411295e 425c452b

drivers/gpu/drm/amd/acp/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -2,6 +2,7 @@ menu "ACP (Audio CoProcessor) Configuration" 


config DRM_AMD_ACP

       bool "Enable AMD Audio CoProcessor IP support"

       depends on DRM_AMDGPU

       select MFD_CORE

       select PM_GENERIC_DOMAINS if PM

       help

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+2 −0
Original line number Diff line number Diff line
@@ -602,6 +602,8 @@ int amdgpu_sync_wait(struct amdgpu_sync *sync); 
void amdgpu_sync_free(struct amdgpu_sync *sync);

int amdgpu_sync_init(void);

void amdgpu_sync_fini(void);

int amdgpu_fence_slab_init(void);

void amdgpu_fence_slab_fini(void);



/*

 * GART structures, functions & helpers

drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c

+5 −5
Original line number Diff line number Diff line
@@ -194,6 +194,7 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 
				bpc = 8;

				DRM_DEBUG("%s: HDMI deep color 10 bpc exceeds max tmds clock. Using %d bpc.\n",

					  connector->name, bpc);

			}

		} else if (bpc > 8) {

			/* max_tmds_clock missing, but hdmi spec mandates it for deep color. */

			DRM_DEBUG("%s: Required max tmds clock for HDMI deep color missing. Using 8 bpc.\n",
@@ -201,7 +202,6 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) 
			bpc = 8;

		}

	}

	}



	if ((amdgpu_deep_color == 0) && (bpc > 8)) {

		DRM_DEBUG("%s: Deep color disabled. Set amdgpu module param deep_color=1 to enable.\n",

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

+21 −4
Original line number Diff line number Diff line
@@ -50,9 +50,11 @@ 
 * KMS wrapper.

 * - 3.0.0 - initial driver

 * - 3.1.0 - allow reading more status registers (GRBM, SRBM, SDMA, CP)

 * - 3.2.0 - GFX8: Uses EOP_TC_WB_ACTION_EN, so UMDs don't have to do the same

 *           at the end of IBs.

 */

#define KMS_DRIVER_MAJOR	3

#define KMS_DRIVER_MINOR	1

#define KMS_DRIVER_MINOR	2

#define KMS_DRIVER_PATCHLEVEL	0



int amdgpu_vram_limit = 0;
@@ -279,14 +281,26 @@ static const struct pci_device_id pciidlist[] = { 
	{0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},

	/* Polaris11 */

	{0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	{0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},

	/* Polaris10 */

	{0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},

	{0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},



	{0, 0, 0}

};
@@ -563,9 +577,12 @@ static struct pci_driver amdgpu_kms_pci_driver = { 
	.driver.pm = &amdgpu_pm_ops,

};







static int __init amdgpu_init(void)

{

	amdgpu_sync_init();

	amdgpu_fence_slab_init();

	if (vgacon_text_force()) {

		DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");

		return -EINVAL;
@@ -576,7 +593,6 @@ static int __init amdgpu_init(void) 
	driver->driver_features |= DRIVER_MODESET;

	driver->num_ioctls = amdgpu_max_kms_ioctl;

	amdgpu_register_atpx_handler();



	/* let modprobe override vga console setting */

	return drm_pci_init(driver, pdriver);

}
@@ -587,6 +603,7 @@ static void __exit amdgpu_exit(void) 
	drm_pci_exit(driver, pdriver);

	amdgpu_unregister_atpx_handler();

	amdgpu_sync_fini();

	amdgpu_fence_slab_fini();

}



module_init(amdgpu_init);

drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

+15 −12
Original line number Diff line number Diff line
@@ -55,8 +55,21 @@ struct amdgpu_fence { 
};



static struct kmem_cache *amdgpu_fence_slab;

static atomic_t amdgpu_fence_slab_ref = ATOMIC_INIT(0);



int amdgpu_fence_slab_init(void)

{

	amdgpu_fence_slab = kmem_cache_create(

		"amdgpu_fence", sizeof(struct amdgpu_fence), 0,

		SLAB_HWCACHE_ALIGN, NULL);

	if (!amdgpu_fence_slab)

		return -ENOMEM;

	return 0;

}



void amdgpu_fence_slab_fini(void)

{

	kmem_cache_destroy(amdgpu_fence_slab);

}

/*

 * Cast helper

 */
@@ -396,13 +409,6 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring, 
 */

int amdgpu_fence_driver_init(struct amdgpu_device *adev)

{

	if (atomic_inc_return(&amdgpu_fence_slab_ref) == 1) {

		amdgpu_fence_slab = kmem_cache_create(

			"amdgpu_fence", sizeof(struct amdgpu_fence), 0,

			SLAB_HWCACHE_ALIGN, NULL);

		if (!amdgpu_fence_slab)

			return -ENOMEM;

	}

	if (amdgpu_debugfs_fence_init(adev))

		dev_err(adev->dev, "fence debugfs file creation failed\n");
@@ -437,13 +443,10 @@ void amdgpu_fence_driver_fini(struct amdgpu_device *adev) 
		amd_sched_fini(&ring->sched);

		del_timer_sync(&ring->fence_drv.fallback_timer);

		for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)

			fence_put(ring->fence_drv.fences[i]);

			fence_put(ring->fence_drv.fences[j]);

		kfree(ring->fence_drv.fences);

		ring->fence_drv.initialized = false;

	}



	if (atomic_dec_and_test(&amdgpu_fence_slab_ref))

		kmem_cache_destroy(amdgpu_fence_slab);

}



/**